On 02/18/2015 10:44 PM, Bill Hart wrote:
> Thanks for the feedback. I'll add it to the ticket.
>
> I don't know off the top of my head what could be going wrong.
The attached patch works for me on x86 as well as x86_64 with ABI=32.
(cf. http://trac.sagemath.org/ticket/17806#comment:6)
Cheers,
-leif
--
You received this message because you are subscribed to the Google Groups
"mpir-devel" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to mpir-devel+unsubscr...@googlegroups.com.
To post to this group, send email to mpir-devel@googlegroups.com.
Visit this group at http://groups.google.com/group/mpir-devel.
For more options, visit https://groups.google.com/d/optout.
--- mpir-2.7.0-alpha12/mpn/x86/fat/fat.c.orig 2014-09-14 21:59:13.000000000 +0200
+++ mpir-2.7.0-alpha12/mpn/x86/fat/fat.c 2015-02-20 20:16:13.909300216 +0100
@@ -37,6 +37,8 @@
long __gmpn_cpuid __GMP_PROTO ((char dst[12], int id));
struct cpuvec_t __gmpn_cpuvec = {
+ __MPN(add_err1_n_init),
+ __MPN(add_err2_n_init),
__MPN(add_n_init),
__MPN(addmul_1_init),
__MPN(copyd_init),
@@ -55,11 +57,14 @@
__MPN(modexact_1c_odd_init),
__MPN(mul_1_init),
__MPN(mul_basecase_init),
+ __MPN(mulmid_basecase_init),
__MPN(preinv_divrem_1_init),
__MPN(preinv_mod_1_init),
__MPN(redc_1_init),
__MPN(rshift_init),
__MPN(sqr_basecase_init),
+ __MPN(sub_err1_n_init),
+ __MPN(sub_err2_n_init),
__MPN(sub_n_init),
__MPN(submul_1_init),
__MPN(sumdiff_n_init),
@@ -102,6 +107,8 @@
#define CPUSETUP_nehalem CPUVEC_SETUP_nehalem
#define CPUSETUP_westmere CPUVEC_SETUP_nehalem
#define CPUSETUP_sandybridge CPUVEC_SETUP_nehalem
+#define CPUSETUP_ivybridge CPUVEC_SETUP_nehalem
+#define CPUSETUP_haswell CPUVEC_SETUP_nehalem
#define CPUSETUP_atom CPUVEC_SETUP_p6;CPUVEC_SETUP_p6_mmx;CPUVEC_SETUP_p6_p3mmx
#define CPUSETUP_nano CPUVEC_SETUP_p6;CPUVEC_SETUP_p6_mmx;CPUVEC_SETUP_p6_p3mmx
#define CPUSETUP_pentium4 CPUVEC_SETUP_pentium4;CPUVEC_SETUP_pentium4_mmx;CPUVEC_SETUP_pentium4_sse2
@@ -116,6 +123,7 @@
#define CPUSETUP_k102 CPUVEC_SETUP_k7;CPUVEC_SETUP_k7_mmx;CPUVEC_SETUP_k7_mmx_k8;CPUVEC_SETUP_k7_mmx_k8_k10;CPUVEC_SETUP_k7_mmx_k8_k10_k102
#define CPUSETUP_k103 CPUVEC_SETUP_k7;CPUVEC_SETUP_k7_mmx;CPUVEC_SETUP_k7_mmx_k8;CPUVEC_SETUP_k7_mmx_k8_k10;CPUVEC_SETUP_k7_mmx_k8_k10_k102
#define CPUSETUP_bulldozer CPUVEC_SETUP_k7;CPUVEC_SETUP_k7_mmx;CPUVEC_SETUP_k7_mmx_k8;CPUVEC_SETUP_k7_mmx_k8_k10;CPUVEC_SETUP_k7_mmx_k8_k10_k102
+#define CPUSETUP_piledriver CPUVEC_SETUP_k7;CPUVEC_SETUP_k7_mmx;CPUVEC_SETUP_k7_mmx_k8;CPUVEC_SETUP_k7_mmx_k8_k10;CPUVEC_SETUP_k7_mmx_k8_k10_k102
#define CPUSETUP_bobcat CPUVEC_SETUP_k7;CPUVEC_SETUP_k7_mmx;CPUVEC_SETUP_k7_mmx_k8;CPUVEC_SETUP_k7_mmx_k8_k10;CPUVEC_SETUP_k7_mmx_k8_k10_k102
#define CPUSETUP_viac3 do{}while(0)
#define CPUSETUP_viac32 do{}while(0)
