"flag" should be marked volatile, otherwise the optimiser may see it never
changes inside the body of the loop and omit checking the flag entirely.
- Wayne
> On 9 Nov 2015, at 08:01, Ian Chapman <ichap...@videotron.ca> wrote:
>
> Hi all,
> I'm having difficulty understanding this situation.
> flag = 1;
> while ( 0 != flag )
> {
> code;
> }
> generates strange assembly code till I commented out
> // flag = 1;
> it looked to me like the optimizer realized that from then on the code
> would be planted in a " $ jmp $; " situation. I intended flag to be
> cleared after an ADC interrupt. ie set flag and wait for it to be cleared.
> Test code snippet and Makefile follow.
>
> Any comment greatly appreciated. Ian.
>
> /* Test of while loop msp430 version of gnu c */
>
> #include <msp430.h>
> void funct1(void);
> int flag, temp, temp2;
>
> int main(void)
> {
> WDTCTL = WDTPW + WDTHOLD; // Disable watchdog timer
> // Internal clock to 8MHz
> DCOCTL = CALDCO_1MHZ; //Page 3 device specific data sheet.
> BCSCTL1 = CALBC1_1MHZ; // ---"""---
> BCSCTL2 = 0;
> BCSCTL3 = 0;
> // flag = 1; //The optimization makes a mess till I commented this out.
> temp = 0;
>
> while( 0 != flag ) //flag = 0 from Interrupt routine.
> {
> temp2 ++; //This did not help
> }
>
> funct1();
> temp2 = temp;
> return 1;
> }
>
> void funct1(void) {
> temp ++;
> }
>
> Makefile
> CC=msp430-gcc
> CFLAGS=-Os -Wall -g -mmcu=msp430g2553
> #CFLAGS=-Os -Wall -g -mmcu=msp430f5438a
> OBJ = while.o
> %.o: %.c $(DEPS)
> $(CC) -c -o $@ $< $(CFLAGS)
> while: $(OBJ)
> $(CC) -o $@.elf $^ $(CFLAGS)
> Dis assembly
> main:
> 0c03e: b2 40 80 5a 20 01 MOV #0x5a80, &0x0120
> 0c044: d2 42 fe 10 56 00 MOV.B &0x10fe, &0x0056
> 0c04a: d2 42 ff 10 57 00 MOV.B &0x10ff, &0x0057
> 0c050: c2 43 58 00 CLR.B &0x0058
> 0c054: c2 43 53 00 CLR.B &0x0053
> 0c058: 92 43 02 02 MOV #0x0001, &flag
> 0c05c: 82 43 04 02 CLR &temp
> 0c060: ff 3f JMP 0xc060 //Planted
> 0c062: 32 d0 f0 00 BIS #0x00f0, SR //Clks/cpu off?
> 0c066: fd 3f JMP 0xc062
> 0c068: 30 40 72 c0 BR #0xc072
> funct1:
> 0c06c: 92 53 04 02 INC &temp
> 0c070: 30 41 RET
> 0c072: 00 13 RETI
> 0c074: ff ff ff ff AND.B @R15+, 0xffff(R15)
> 0c078: ff ff
> (mspdebug)
>
>
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