G'Day All, I have discovered a bug in the "adc12.h" header file. (After debugging an ADC app for many hours!)
The file erroneously has the following #define SHS_0 0 #define SHS_1 (1<<6) #define SHS_2 (2<<6) #define SHS_3 (3<<6) but the SHS bits live at bits 10 and 11, so the file should read as below #define SHS_0 0 #define SHS_1 (1<<10) #define SHS_2 (2<<10) #define SHS_3 (3<<10) I don't know if attachments work for the mailing last, so I will not attempt to attach my "upgraded" header file. But, if will repeat the entire modified file, so "cut" and "paste" can be used to replace the offending header file for now. //-------------------------------------------------------------------------- -------------- Cut below #ifndef __msp430_headers_adc12_h #define __msp430_headers_adc12_h /* adc12.h * * mspgcc project: MSP430 device headers * ADC12 module header * * (c) 2002 by M. P. Ashton <d...@ieee.org> * Originally based in part on work by Texas Instruments Inc. * * $Id: adc12.h,v 1.3 2002/06/18 16:41:35 data Exp $ */ /* Switches: none */ #define ADC12CTL0_ 0x01A0 /* ADC12 Control 0 */ sfrw(ADC12CTL0,ADC12CTL0_); #define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */ sfrw(ADC12CTL1,ADC12CTL1_); #define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */ sfrw(ADC12IFG,ADC12IFG_); #define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */ sfrw(ADC12IE,ADC12IE_); #define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */ sfrw(ADC12IV,ADC12IV_); #define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */ #ifdef _GNU_ASSEMBLER_ #define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */ #else #define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ #endif #define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */ sfrw(ADC12MEM0,ADC12MEM0_); #define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */ sfrw(ADC12MEM1,ADC12MEM1_); #define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */ sfrw(ADC12MEM2,ADC12MEM2_); #define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */ sfrw(ADC12MEM3,ADC12MEM3_); #define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */ sfrw(ADC12MEM4,ADC12MEM4_); #define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */ sfrw(ADC12MEM5,ADC12MEM5_); #define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */ sfrw(ADC12MEM6,ADC12MEM6_); #define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */ sfrw(ADC12MEM7,ADC12MEM7_); #define ADC12MEM8_ 0x0150 /* ADC12 Conversion Memory 8 */ sfrw(ADC12MEM8,ADC12MEM8_); #define ADC12MEM9_ 0x0152 /* ADC12 Conversion Memory 9 */ sfrw(ADC12MEM9,ADC12MEM9_); #define ADC12MEM10_ 0x0154 /* ADC12 Conversion Memory 10 */ sfrw(ADC12MEM10,ADC12MEM10_); #define ADC12MEM11_ 0x0156 /* ADC12 Conversion Memory 11 */ sfrw(ADC12MEM11,ADC12MEM11_); #define ADC12MEM12_ 0x0158 /* ADC12 Conversion Memory 12 */ sfrw(ADC12MEM12,ADC12MEM12_); #define ADC12MEM13_ 0x015A /* ADC12 Conversion Memory 13 */ sfrw(ADC12MEM13,ADC12MEM13_); #define ADC12MEM14_ 0x015C /* ADC12 Conversion Memory 14 */ sfrw(ADC12MEM14,ADC12MEM14_); #define ADC12MEM15_ 0x015E /* ADC12 Conversion Memory 15 */ sfrw(ADC12MEM15,ADC12MEM15_); #define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */ #ifdef _GNU_ASSEMBLER_ #define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */ #else #define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ #endif #define ADC12MCTL0_ ADC12MCTL_ /* ADC12 Memory Control 0 */ sfrb(ADC12MCTL0,ADC12MCTL0_); #define ADC12MCTL1_ 0x0081 /* ADC12 Memory Control 1 */ sfrb(ADC12MCTL1,ADC12MCTL1_); #define ADC12MCTL2_ 0x0082 /* ADC12 Memory Control 2 */ sfrb(ADC12MCTL2,ADC12MCTL2_); #define ADC12MCTL3_ 0x0083 /* ADC12 Memory Control 3 */ sfrb(ADC12MCTL3,ADC12MCTL3_); #define ADC12MCTL4_ 0x0084 /* ADC12 Memory Control 4 */ sfrb(ADC12MCTL4,ADC12MCTL4_); #define ADC12MCTL5_ 0x0085 /* ADC12 Memory Control 5 */ sfrb(ADC12MCTL5,ADC12MCTL5_); #define ADC12MCTL6_ 0x0086 /* ADC12 Memory Control 6 */ sfrb(ADC12MCTL6,ADC12MCTL6_); #define ADC12MCTL7_ 0x0087 /* ADC12 Memory Control 7 */ sfrb(ADC12MCTL7,ADC12MCTL7_); #define ADC12MCTL8_ 0x0088 /* ADC12 Memory Control 8 */ sfrb(ADC12MCTL8,ADC12MCTL8_); #define ADC12MCTL9_ 0x0089 /* ADC12 Memory Control 9 */ sfrb(ADC12MCTL9,ADC12MCTL9_); #define ADC12MCTL10_ 0x008A /* ADC12 Memory Control 10 */ sfrb(ADC12MCTL10,ADC12MCTL10_); #define ADC12MCTL11_ 0x008B /* ADC12 Memory Control 11 */ sfrb(ADC12MCTL11,ADC12MCTL11_); #define ADC12MCTL12_ 0x008C /* ADC12 Memory Control 12 */ sfrb(ADC12MCTL12,ADC12MCTL12_); #define ADC12MCTL13_ 0x008D /* ADC12 Memory Control 13 */ sfrb(ADC12MCTL13,ADC12MCTL13_); #define ADC12MCTL14_ 0x008E /* ADC12 Memory Control 14 */ sfrb(ADC12MCTL14,ADC12MCTL14_); #define ADC12MCTL15_ 0x008F /* ADC12 Memory Control 15 */ sfrb(ADC12MCTL15,ADC12MCTL15_); #define ADC12SC 0x001 /* ADC12CTL0 */ #define ENC 0x002 #define ADC12TOVIE 0x004 #define ADC12OVIE 0x008 #define ADC12ON 0x010 #define REFON 0x020 #define REF2_5V 0x040 #define MSH 0x080 #define MSC 0x080 #define SHT0_0 0 #define SHT0_1 0x100 #define SHT0_2 0x200 #define SHT0_3 0x300 #define SHT0_4 0x400 #define SHT0_5 0x500 #define SHT0_6 0x600 #define SHT0_7 0x700 #define SHT0_8 0x800 #define SHT0_9 0x900 #define SHT0_10 0xA00 #define SHT0_11 0xB00 #define SHT0_12 0xC00 #define SHT0_13 0xD00 #define SHT0_14 0xE00 #define SHT0_15 0xF00 #define SHT1_0 0x0000 #define SHT1_1 0x1000 #define SHT1_2 0x2000 #define SHT1_3 0x3000 #define SHT1_4 0x4000 #define SHT1_5 0x5000 #define SHT1_6 0x6000 #define SHT1_7 0x7000 #define SHT1_8 0x8000 #define SHT1_9 0x9000 #define SHT1_10 0xA000 #define SHT1_11 0xB000 #define SHT1_12 0xC000 #define SHT1_13 0xD000 #define SHT1_14 0xE000 #define SHT1_15 0xF000 #define ADC12BUSY 0x0001 /* ADC12CTL1 */ #define CONSEQ_0 0 #define CONSEQ_1 2 #define CONSEQ_2 4 #define CONSEQ_3 6 #define ADC12SSEL_0 0 #define ADC12SSEL_1 (1<<3) #define ADC12SSEL_2 (2<<3) #define ADC12SSEL_3 (3<<3) #define ADC12DIV_0 0 #define ADC12DIV_1 (1<<5) #define ADC12DIV_2 (2<<5) #define ADC12DIV_3 (3<<5) #define ADC12DIV_4 (4<<5) #define ADC12DIV_5 (5<<5) #define ADC12DIV_6 (6<<5) #define ADC12DIV_7 (7<<5) #define ISSH 0x0100 #define SHP 0x0200 #define SHS_0 0 #define SHS_1 (1<<10) #define SHS_2 (2<<10) #define SHS_3 (3<<10) #define CSTARTADD_0 0 #define CSTARTADD_1 (1<<12) #define CSTARTADD_2 (2<<12) #define CSTARTADD_3 (3<<12) #define CSTARTADD_4 (4<<12) #define CSTARTADD_5 (5<<12) #define CSTARTADD_6 (6<<12) #define CSTARTADD_7 (7<<12) #define CSTARTADD_8 (8<<12) #define CSTARTADD_9 (9<<12) #define CSTARTADD_10 (10<<12) #define CSTARTADD_11 (11<<12) #define CSTARTADD_12 (12<<12) #define CSTARTADD_13 (13<<12) #define CSTARTADD_14 (14<<12) #define CSTARTADD_15 (15<<12) #define INCH_0 0 /* ADC12CTLx */ #define INCH_1 1 #define INCH_2 2 #define INCH_3 3 #define INCH_4 4 #define INCH_5 5 #define INCH_6 6 #define INCH_7 7 #define INCH_8 8 #define INCH_9 9 #define INCH_10 10 #define INCH_11 11 #define INCH_12 12 #define INCH_13 13 #define INCH_14 14 #define INCH_15 15 #define SREF_0 0 #define SREF_1 (1<<4) #define SREF_2 (2<<4) #define SREF_3 (3<<4) #define SREF_4 (4<<4) #define SREF_5 (5<<4) #define SREF_6 (6<<4) #define SREF_7 (7<<4) #define EOS 0x80 #endif //-------------------------------------------------------------------------- -------------- Cut above Cheers Harry R. Lemmens hlemm...@optushome.com.au (Preferred email address)