Chris Liechti wrote:
Am 13.12.2002 18:42:36, schrieb Celso Providelo <cp...@terra.com.br>:
I've found problems to setup the timer B to use the pulse in the TBCLK
as the clock source
P4DIR &= ~BIT7;
P4SEL |= BIT7;
TBCTL = TBSSEL0 + ID0 + TBCLR;
TBSSEL0 -> value of 1 -> ACLK
you can use TBSSEL_0 (underline!) to select TBCLK or leave at away as it has
the value of 0 anyway.
and a GCC feature:
#define TBSSEL_TBCLK TBSSEL_0
#define TBSSEL_ACLK TBSSEL_1
#define TBSSEL_SMCLK TBSSEL_2
#define TBSSEL_INCLK TBSSEL_3
are defined, so that you can also write
TBCTL = TBSSEL_TBCLK + ID0 + TBCLR;
TBCTL |= MC0;
chris
Just to br emphatic about what I missapplied in this application, the
correct initialization code follows:
/* set SSEL=0, 16 bit length, Input divider in /1, and clear the TBR */
TBCTL = TBSSEL_0 + TBCLR;
/* set the TBCL0 register via TBCCR0, it should be the maximum value
counted by the timer; it was zero and means that the timer is halted by
default. */
TBCCR0 = 15;
/* start to run in up-mode 0 < TBR < TBCL0. */
TBCTL |= MC0 ;
/* connect timer module bit correspondent to TBCLK to the timer.port P4.*/
P4SEL |= BIT7;
/*set the timer.port P4 pin direction as input . */
P4DIR &= ~BIT7;
regards.
--
Celso Providelo
cp...@terra.com.br
Linux user #166906
GNUsp Project
LAMI-Laboratories of Microprocessors
Department of Electrical Engineering
University of Sao Paulo (USP - Sao Carlos)
