Hi,
Am Sonntag, 12.09.04 um 15:57 Uhr schrieb Chris Liechti:
As I wrote playing with the ccr settings was not successful so far.
you cant invert the signal in the hardware, but you can invert the bit
before shifting in: invert the carry bit:
xor #BIT0, r2 ; inverted input
or you can invert the whole byte at the end, which is probably better,
performance wise.
inverting the interrupt edge for the startbit detection should be
trivial too.
chris
Yes I tried this but there seems to be more necessary than just
inverting the tx byte. If I invert the tx byte and want to send a 'H' =
0x48 = 0100 1000b with start and stop bits the following bits are
sended:
1 0100 1000 0. The tx signal is low active and I can measure about
1.7ms for the 4 zeros at 2400 Baud, which is ok.
When inverted the bits I send 0 1011 0111 1. Again I would expect about
1.7ms for the four ones. But now I measure about 2.2 ms.
I assume there is something wrong with the timer a/capture compare
settings which sends a one for some time before the real bits are
shifted out. This is not relevant in the case where tx is low active.
But now, with the inverted signal it is relevant because the high
prolongs my signal.
Any idea what could be wrong?
Thanks,
Peter
