hi, i am implementing bit-bangign i2c master and slave on the olimex stk2 kits, with the msp430x449 processor.
ive connected the two processors via a IDC header cable on their ext ports. the system is completely interrupt driven. there is a clock which generates interrupts. both the master and slave are interrupt driven by gpio interrupts on the ports assigned to the clock. the master controls the clock. now, the problem im having is with the STOP condition. to START, the slave enables data interrupts (ie. gpio interrupt on the SDA line) and disables the clk interrupts (ie. gpio interrupt on the clk line). when the slave notices the data line go low, it disables the data ints, and enables the clk, and now totally runs on clk interrupts only. everything works fine, receiving, sending, acks etc... in all these states, the data line is changed only when the clk is low, and whoever is reading the data will only read it when the clk is high. however, ive been trying to get it to detect a STOP condn. for the stop condn, the data line will go up while the clk is high. so this is a special condn. to detect this, i enable data ints on the slave, when the clk is high. and disable them when the clk goes low. so, in all states except STOP, the data line should not change while the clk is high. however, the slave is unable to detect this. for every bit exchanged , the slave detects the data int, and says that it has received a stop condn. but this should not happen, right, coz the data line is not changing, while the clk is high. i have read the user guide and all there was in it about interrupts, but have not been able to figure out why my soln should not work. could you give me any ideas on this? is there some delay involved, should the slave wait b4 enabling data ints when the clk goes high? if required, ill post my code here. not posting it now, coz its pretty long. thanks, karan CM II Resolution Systems Inc.
