Thanks Rick, That is exactly the info I needed. Normally I would cut a lot for a reply, but this is too important. I have two boards, one with the analog stuff and a digital board with the msp, an mmc card, an irda chip, and an LCD. Both have ground planes. They are tied together with a molex .5mm flex cable. I bring out AVss and DVss and tie them together on the analog board, which supplies AVcc. I put a .1uF across AVss and AVcc on the digital board and put the 10uF + another .1uF cap from AVcc to analog ground on the analog board at the connector. DVcc is supplied by a TI TPS79730 on the digital board. AVcc is supplied by a MAX6129EUK30 .04% 3V reference on the analog board, so they should be pretty close. The peripherals have separate supplies.
Rick Jenkins wrote: > > On Sunday 10 October 2004 22:06, Garst R. Reese wrote: > > > The connection examples for these two supply voltages all show them > > externally tied together. Can they actually be separate supplies with > > different voltages? I assumed they could be, but got worried when I > > could not find an example. > > If you are actually using the analog facilities on the chip, performance will > be poor if these are merely tied. My experience is that careful filtering of > AVCC is necessary, both for the comparator and for the ADC12. Poor > decoupling of DVCC is a wonderful way to get exotic, erratic, and > non-repeatable bugs, as a look through the archives of this mailing list > would show. If you don't need the analogue stuff, tie the supplies together > and dcouple them as one. > > The AVCC and DVCC voltages should be nominally equal, though a difference of > a few tens of millivolts seems not to matter. > > > >Murata, AVX, and Kemet all show 0805 10uF 6V 10% Ceramic capacitors. > > >Would these require the extra 0.1uF? > > Yes. I've tried it. > > The large ceramics have enough intrinsic inductance to resonate at a > surprisingly low frequency, and the 0.1uF takes care of high-frequency > decoupling. No free ride here, I'm afraid. The 0.1uF must be as close to > the chip as you can get it, but a centimeter or so of total lead length on > the 10uF is OK. This can be used to advantage to "isolate" the two > capacitors, so that you don't need separate traces to the chip pins, and it > eases layout too. > > -- > Rick Jenkins <r...@hartmantech.com> > Hartman Technica http://www.hartmantech.com > Phone +1 (403) 230-1987 voice & fax > 221 35 Avenue. N.E., Calgary, Alberta, Canada T2E 2K5
