you're right. Now, after knowing the problem and following your
user guide 'reading guide' I'm also able to see some hints in the
documentation.
but now I'm wondering about the next thing:
In my opinion there are two different descriptions of the
ADC10B1 bit. It is used in DTC two block transfer mode to indicate
which block was filled.
The section about Two-Block Transfer Mode writes:
...
At this point, block one is full
and both the ADC10IFG flag the ADC10B1 bit are set. The user can test the
ADC10B1 bit to determine that block one is full.
...
After n transfers have
completed, block two is full. The ADC10IFG flag is set and the ADC10B1 bit
is cleared. User software can test the cleared ADC10B1 bit to determine that
block two is full.
...
and the ADC10DTC0 Register Description says:
ADC10B1 - ADC10 block one.
This bit indicates for two-block mode which block is filled
with ADC10 conversion results. ADC10B1 is valid only after ADC10IFG has
been set the first time during DTC operation. ADC10TB must also be set
0 Block 1 is filled
1 Block 2 is filled
my software test showed up that the Two-Block Transfer Mode section is
correct and the ADC10DTC0 Register Description seems to be wrong.
In my understanding these two descriptions are conflicting.
What do you think ?
thanks,
matthias
m...@horizon.com schrieb:
; CAVEAT below !!!!!!
; you have to write the number of transfers before giving the
; buffer address or it won't start transfers
Guess in which order I tried to initialize the DTC - arhhg!
After swapping the initialization of ADC10DTC0 and ADC10DTC1 everything
is working as expected.
Did you figured out this 'rule' by yourself or is this somehow
documented ? I read the ADC10 chapter of the user guide over and over
but I couldn't find anything like this - but after reading through this
more than three times you get a kind of blind anyway ;-)
It's Evil... it's documented in the state transfer diagram,
figure 18-12 (and figure 18-10 for one-block mode).
Notice the three states "DTC reset", "DTC init" and "DTC idle".
First, notice the note by the "DTC reset" state documenting the
short alias "n" for the count register, ADC10DTC1.
To get from 1 to 2, you need to write the count register. Clearing
the count register resets the entire state machine.
To get from 2 to 3, you need to write the ADC10SA register.
On the way, it passes through the "x=n" bubble, where the count is
latched, so the value of the count register at the time you write
ADC10SA is what's going to be used for the first block.
The other hint is the description of ADC10SA:
ADC10SAx Bits ADC10 start address. These bits are the start address for the
DTC. A write
15-1 to register ADC10SA is required to initiate DTC transfers.
Unused Bit 0 Unused, Read only. Always read as 0.
Which is reminding you that writing to ADC10SA should be the last thing
you do.
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