Hi Oszkar,
The latest compiler supports the extended CPU; the problem is actually in the
linker--I can't seem to make it recognise both chunks of code space (that below
and above the vectors). Below is my original posting. I'm hoping someone
knows the answer now.
William
-------- Original Message --------
Date: Thu, 15 Mar 2007 19:06:06 -0700
From: [email protected]
To: [email protected]
Hi All,
I have been using msp430-gcc for several years now and have just started using
the MSP430FG4618 with the mspgcc-win32 20070216 distribution. The ld script
MEMORY configuration for this chip looks like this:
MEMORY
{
text (rx) : ORIGIN = 0x3100, LENGTH = 0xcec0
data (rwx) : ORIGIN = 0x1100, LENGTH = 0x2000
vectors (rw) : ORIGIN = 0xffc0 LENGTH = 64
bootloader(rx) : ORIGIN = 0x0c00, LENGTH = 1K
infomem(rx) : ORIGIN = 0x1000, LENGTH = 256
infomemnobits(rx) : ORIGIN = 0x1000, LENGTH = 256
}
Note that the 64 kB of program flash starting at 0x10000 is not included, so a
116 kB chip appears to only have 52 kB of code space. I have tried adding
another MEMORY definition as follows:
text2 (rx) : ORIGIN = 0x10000, LENGTH = 0x10000
However, I cannot find any documentation on how to specify multiple text segments in the SECTIONS definitions.
Currently, the .text section that is mapped with "> text" to the program flash below the vectors. I have
tried "> text,text2" and "> text and > text2" but of course they are not proper syntax. I
have also tried a single MEMORY text definition with two origins and two lengths, but the ld syntax doesn't permit that,
either.
Can someone who groks ld enlighten me on how to gain access to the all of the
non-contiguous program flash in the new 'FG46xx chips?
Thank you in advance,
William
Oszkar Ambrus wrote:
Hi there,
I've started working on extending mspgcc to support the MSP430X
architecture,
to support a code size larger than 64K (up to 1Mb).
Has anyone started working on it yet?
Or are there any basic issues I have to keep in mind in extending/adding
gcc instructions?
Best regards,
Oszkar Ambrus
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