(something wrong with mails with attachments in maillist, so reposting without it...)
because of 20-bit addressing in this mcu I've patched the dma.h file. I do not know, if sfrdw() statement exists, so I set up the pairs of SFRs... correct me, if it exists... the code: ---------------------------------------------------------- #define DMA0CTL_ 0x01E0 /* DMA channel 0 control */ sfrw(DMA0CTL, DMA0CTL_); #define DMA0SA_ 0x01E2 /* DMA channel 0 source address */ sfrw(DMA0SA, DMA0SA_); #define DMA0DA_ 0x01E4 /* DMA channel 0 destination address */ sfrw(DMA0DA, DMA0DA_); #define DMA0SZ_ 0x01E6 /* DMA channel 0 transfer size */ sfrw(DMA0SZ, DMA0SZ_); #define DMA1CTL_ 0x01E8 /* DMA channel 1 control */ sfrw(DMA1CTL, DMA1CTL_); #define DMA1SA_ 0x01EA /* DMA channel 1 source address */ sfrw(DMA1SA, DMA1SA_); #define DMA1DA_ 0x01EC /* DMA channel 1 destination address */ sfrw(DMA1DA, DMA1DA_); #define DMA1SZ_ 0x01EE /* DMA channel 1 transfer size */ sfrw(DMA1SZ, DMA1SZ_); #define DMA2CTL_ 0x01F0 /* DMA channel 2 control */ sfrw(DMA2CTL, DMA2CTL_); #define DMA2SA_ 0x01F2 /* DMA channel 2 source address */ sfrw(DMA2SA, DMA2SA_); #define DMA2DA_ 0x01F4 /* DMA channel 2 destination address */ sfrw(DMA2DA, DMA2DA_); #define DMA2SZ_ 0x01F6 /* DMA channel 2 transfer size */ sfrw(DMA2SZ, DMA2SZ_); ---------------------------------------------------------- should be replaced with: ---------------------------------------------------------- #ifdef __MSP430_HAS_DMAX_3__ #define DMAIV_ 0x0126 /* DMA interrupt vector */ sfrw(DMAIV, DMAIV_); #define DMA0CTL_ 0x01D0 /* DMA channel 0 control */ sfrw(DMA0CTL, DMA0CTL_); #define DMA0SAL_ 0x01D2 /* DMA channel 0 source address low*/ sfrw(DMA0SAL, DMA0SAL_); #define DMA0SAH_ 0x01D4 /* DMA channel 0 source address high*/ sfrw(DMA0SAH, DMA0SAH_); #define DMA0DAL_ 0x01D6 /* DMA channel 0 destination address low*/ sfrw(DMA0DAL, DMA0DAL_); #define DMA0DAH_ 0x01D8 /* DMA channel 0 destination address high*/ sfrw(DMA0DAH, DMA0DAH_); #define DMA0SZ_ 0x01DA /* DMA channel 0 transfer size */ sfrw(DMA0SZ, DMA0SZ_); #define DMA1CTL_ 0x01DC /* DMA channel 1 control */ sfrw(DMA1CTL, DMA1CTL_); #define DMA1SAL_ 0x01DE /* DMA channel 1 source address low*/ sfrw(DMA1SAL, DMA1SAL_); #define DMA1SAH_ 0x01E0 /* DMA channel 1 source address high*/ sfrw(DMA1SAH, DMA1SAH_); #define DMA1DAL_ 0x01E2 /* DMA channel 1 destination address low*/ sfrw(DMA1DAL, DMA1DAL_); #define DMA1DAH_ 0x01E4 /* DMA channel 1 destination address high*/ sfrw(DMA1DAH, DMA1DAH_); #define DMA1SZ_ 0x01E6 /* DMA channel 1 transfer size */ sfrw(DMA1SZ, DMA1SZ_); #define DMA2CTL_ 0x01E8 /* DMA channel 2 control */ sfrw(DMA2CTL, DMA2CTL_); #define DMA2SAL_ 0x01EA /* DMA channel 2 source address low*/ sfrw(DMA2SAL, DMA2SAL_); #define DMA2SAH_ 0x01EC /* DMA channel 2 source address high*/ sfrw(DMA2SAH, DMA2SAH_); #define DMA2DAL_ 0x01EE /* DMA channel 2 destination address */ sfrw(DMA2DAL, DMA2DAL_); #define DMA2DAH_ 0x01F0 /* DMA channel 2 destination address */ sfrw(DMA2DAH, DMA2DAH_); #define DMA2SZ_ 0x01F2 /* DMA channel 2 transfer size */ sfrw(DMA2SZ, DMA2SZ_); #else //__MSP430_HAS_DMAX_3__ #define DMA0CTL_ 0x01E0 /* DMA channel 0 control */ sfrw(DMA0CTL, DMA0CTL_); #define DMA0SA_ 0x01E2 /* DMA channel 0 source address */ sfrw(DMA0SA, DMA0SA_); #define DMA0DA_ 0x01E4 /* DMA channel 0 destination address */ sfrw(DMA0DA, DMA0DA_); #define DMA0SZ_ 0x01E6 /* DMA channel 0 transfer size */ sfrw(DMA0SZ, DMA0SZ_); #define DMA1CTL_ 0x01E8 /* DMA channel 1 control */ sfrw(DMA1CTL, DMA1CTL_); #define DMA1SA_ 0x01EA /* DMA channel 1 source address */ sfrw(DMA1SA, DMA1SA_); #define DMA1DA_ 0x01EC /* DMA channel 1 destination address */ sfrw(DMA1DA, DMA1DA_); #define DMA1SZ_ 0x01EE /* DMA channel 1 transfer size */ sfrw(DMA1SZ, DMA1SZ_); #define DMA2CTL_ 0x01F0 /* DMA channel 2 control */ sfrw(DMA2CTL, DMA2CTL_); #define DMA2SA_ 0x01F2 /* DMA channel 2 source address */ sfrw(DMA2SA, DMA2SA_); #define DMA2DA_ 0x01F4 /* DMA channel 2 destination address */ sfrw(DMA2DA, DMA2DA_); #define DMA2SZ_ 0x01F6 /* DMA channel 2 transfer size */ sfrw(DMA2SZ, DMA2SZ_); #endif ---------------------------------------------------------- -- _____________ Oleg V. Kobrin
