-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Lichen Wang schrieb: > Very interesting observation. > > The source-register address mode field As is only 2-bit wide. (That > means it can only be 00, 01, 10, or 11). How did they manage to support > 7 different address mode?
This can be easily answered... there is the necessary third bit "AD" for the destination. And to be realistic, there are only 6 modes (immediate mode is nothing else than an indirect autoincrement mode). Back to the original question: The first version (MOV #0x1234, x(Rd)) is a three word instruction, the second version (MOV @Rs+, x(Rd)) is a two(!) word instruction. The instruction MOV @R6+, 2(R4) results in (R6 because it's clearer in the resulting opcode): b4 46 02 00 mov @r6+, 2(r4) Same code will appear if you use r0 instead of r6. The first version in your example is a special version of the second one. It writes the necessary value for the constant (0x1234) to the next word address so @R0+ points to this value and increment the PC to the point to the second constant (0x0200). I think there is no way around your problem other than using the first version. The second one doesn't work because you're not able to write your data in the middle of the instruction (where it should be). So it is just a question of the order of your code. By the way: there is no difference in speed and lenght between the two versions (5 cycles, 3 words). > */Maik Heese <[email protected]>/* wrote: > > Dear All, > > I think there is a bug in msp430-as, > which creates wrong binary code for: > > *** @R0+, X(Rm) > > my OS: CentOS release 4.5 > > I build my own toolchain using: > - binutils-2.18 from ftp://sources.redhat.com/pub/binutils/releases/ > - gcc-3.2.3 from ftp://gcc.gnu.org/pub/gcc/releases/ > - patch files gcc-3.3 from http://mspgcc.cvs.sourceforge.net/mspgcc/gcc/ > - msp430-libc from mspgcc.cvs.sourceforge.net:/cvsroot/mspgcc > > ------------------------------------------------------------- > my ASM program: > > MOV #0x1234, 2(R4) > > MOV @R0+, 2(R4) > .word 0x1234 > > ------------------------------------------------------------- > and the disassebled code (msp430-as my.s -o my.o; msp430-objdump -d > my.o): > > my.o: file format elf32-msp430 > > Disassembly of section .text: > > 00000000 <.text>: > 0: b4 40 34 12 mov #4660, 2(r4) ;#0x1234 > 4: 02 00 > 6: b4 40 02 00 mov #2, 4660(r4);#0x0002 > a: 34 12 > > ------------------------------------------------------------- > > I think the two variants should be equivalent, but > the asm code of *** @R0+, X(Rm) creates wrong ordered > arguments in binary code. > > Best regards, > Maik Mit freundlichen Grüßen / Best regards Robert Dominicus-Schleutermann Software + Systeme Erfurt GmbH Fichtenweg 8 99198 Erfurt-Kerspleben Tel. : +49 (0)36203 96314 Fax : +49 (0)36203 96333 E-Mail : [email protected] Web : www.sse-erfurt.de www.cellvas.de www.mobilog.de Handelsregister Erfurt: HRB 1604 Geschäftsführer: Dr. Dietrich Mandler, Uwe-Jens Tietz, Wilfried Dietrich -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.4 (MingW32) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFG55Qj7kPn7znKZuYRAsGQAJ0VvKaCcHAMefQCg/yCtBmKVbeaUwCfaXlT Ncxw0vEcrzN4JyIhLgLq8ko= =hdVa -----END PGP SIGNATURE-----
