Radiation bit flips are of course a concern, but I think you concentrate on a pretty improbable case. Why worry about this particular bit flip when there are so many other locations that could be changed (registers, memory, internal state) that would result in other random application failures. If you are concerned about radiation flips you have to implement watchdogs or even periodic resets.
To put some numbers on it and give you an idea on the relative probability of such events, we had an application in a slightly elevated radiation field, where a 4MB memory array would get several bit flips a week. We dealt with it by checksumming the data so that we knew which bit flipped and flipping it back. On 6/30/08, Hardy Griech <[email protected]> wrote: > Chris Liechti wrote: > : > > no it isn't checksum protected. halting the CPU is also described in the > > slaa149 application note. > > : > > ok, I've read it and my concern is still, that some bit flipping due to > radiation or other effects my put the msp430 into JTAG halt mode. If I > understood slaa149 correctly TCE1 and/or HALT_JTAG in the "JTAG Control > Signal Register" are required to stop the CPU. That means a maximum of > two bit flips which must not be timely simultaneous! > > Any known application note which describes behaviour of the internal > MSP430 registers on radiation (this leads to my refresh question!)? > > Thanks > > > Hardy > > > ------------------------------------------------------------------------- > Check out the new SourceForge.net Marketplace. > It's the best place to buy or sell services for > just about anything Open Source. > http://sourceforge.net/services/buy/index.php > _______________________________________________ > Mspgcc-users mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/mspgcc-users >
