----- Ursprüngliche Nachricht ----- Von: JMGross An: MSPGCC mailing list, Gesendet am: 25 Feb 2009 13:05:46 Betreff: Re: [Mspgcc-users] error w/msp430x54xx.h in win release mspgcc-20081230.exe > swallen wrote: >> WDT_A register is defined wrong per the datasheet (). >> >> from the listing: >> 00000150 l *ABS* 00000000 WDTCTL >> >> from datasheet (SLAS612–SEPTEMBER 2008): >> >> REGISTER BASE OFFSET >> WDTCTL 0150h 0Ch (=0x15C) >> >Yes, you are right. Wrong offset in wdt_a.h. Fixed in repository: >http://mspgcc.cvs.sourceforge.net/viewvc/mspgcc/msp430-libc/include/msp430/wdt_a.h?r1=1.3&r2=1.4 > It's not the only bug in wdt_a.h: > >#define WDTPW (0xA5<<8) > >should read > >#define WDTPW (0x5A<<8) And that's not all in wdt_a.h. After looking closer, I found some wrong comments (the defines are okay): #define WDTIS_0 (0<<0) /* Watchdog timer /64 */ #define WDTIS_1 (1<<0) /* Watchdog timer /512 */ #define WDTIS_2 (2<<0) /* Watchdog timer /8192 */ #define WDTIS_3 (3<<0) /* Watchdog timer /32K */ #define WDTIS_4 (4<<0) /* Watchdog timer /512K */ #define WDTIS_5 (5<<0) /* Watchdog timer /8192K */ #define WDTIS_6 (6<<0) /* Watchdog timer /128M */ #define WDTIS_7 (7<<0) /* Watchdog timer /2G */ should read #define WDTIS_0 (0<<0) /* Watchdog timer /2G */ #define WDTIS_1 (1<<0) /* Watchdog timer /128M */ #define WDTIS_2 (2<<0) /* Watchdog timer /8192K */ #define WDTIS_3 (3<<0) /* Watchdog timer /512K */ #define WDTIS_4 (4<<0) /* Watchdog timer /32K */ #define WDTIS_5 (5<<0) /* Watchdog timer /8192 */ #define WDTIS_6 (6<<0) /* Watchdog timer /512 */ #define WDTIS_7 (7<<0) /* Watchdog timer /64 */ Also, I take a look into sys.h, and #define SYSBSLSIZE_0 (0<<0) /* size 512 bytes, BSL_SEG_3 */ #define SYSBSLSIZE_1 (0<<1) /* size 1024 bytes, BSL_SEG_2,3 */ #define SYSBSLSIZE_2 (0<<2) /* size 1536 bytes, BSL_SEG_1,2,3 */ #define SYSBSLSIZE_3 (0<<3) /* size 2048 bytes, BSL_SEG_0,1,2,3 */ doesn't make much sense. It should better read #define SYSBSLSIZE_0 (0<<0) /* size 512 bytes, BSL_SEG_3 */ #define SYSBSLSIZE_1 (1<<0) /* size 1024 bytes, BSL_SEG_2,3 */ #define SYSBSLSIZE_2 (2<<0) /* size 1536 bytes, BSL_SEG_1,2,3 */ #define SYSBSLSIZE_3 (3<<0) /* size 2048 bytes, BSL_SEG_0,1,2,3 */ (0<<x) doesn't change much for different x :) And while I was already on it, I took the liberty to add some definitions to msp430x54xx.h (byte access to the SFRx registers and the whole SFRRPCR definition) as well as some corrected omments for the interrupt vectors. I don't see any sense in the software configuration of the reset line pullups (if you want the processor to start at all, you'll need external hardware that is compatible with the PUC configuration of that pin, which contradicts any different use of this pin later), but well, if it's there, it shall get honored with some defs. I have attached the altered files JMGross
msp430x54xx.h
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sys.h
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wdt_a.h
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