Hi,
Thanks for response.
On Wed, 2009-04-01 at 14:20 +0200, Roberto Padovani wrote:
> I am doing the same thing with our old projects, going to MSP430F2410.
> Are you using a MSP430X-patched mspgcc built from the latest CVS source ?
Yes, I use the latest CVS.
> If so, you also have to fix a "bug" in the libc, by adding this line
> in your main.c:
>
> void __low_level_init(void);
>
> __attribute__((naked, section(".init3"))) void __low_level_init(void)
> {
> WDTCTL = WDTPW + WDTHOLD;
> // any other low level initialization you want
> }
Shoud I put all hardware initiaization into this function? Configuring
interrupts, etc?
And if it is a bug, may be it make sense to patch the libc?
> If you don't overwrite it, the __low_level_init which is insiede the
> libc will be used.
> And the problem is that in the libc the WDTCTL address is the 0x0120
> of the old MSP430s; the newest ones with MSP430X architecture have the
> WDTCTL at the address 0x015C. The header files for using in your
> program are correct, but they don't affect that single line in the
> libc.
> It took me a while to understand why my firmware was continuosly
> resetting itself :-/
Hm, but it does not seems like firmware is continousy resetting. It
seems like it works, except RX/TX interrupts.
I run the code below under IAR and CrossWorks, both works ok.
But for some reasons, using them it's a big pain wil require significant
code rewriting.
> R#
>
> 2009/4/1 Dmitry Zuikov <[email protected]>:
> > Greetings,
> >
> > Could anybody provide an assistance (not for free, of course) porting
> > our application from MSP430F1612 to MSP430F2418 ?
> >
> > I faced problems even when I try to launch an example from TI site
> > adapted for gcc (code is below).
> >
> > This code works ok under IAR, but there is no any response in port under
> > MSPGCC.
> >
> > I built mspgcc from cvs.
> >
> > code (adapted MSP430x261x_uscia0_uart_03.c )
> > //******************************************************************************
> > // MSP430x26x Demo - USCI_A0, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz
> > ACLK
> > //
> > // Description: Echo a received character, RX ISR used. Normal mode is
> > LPM3,
> > // USCI_A0 RX interrupt triggers TX Echo.
> > // ACLK = BRCLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO ~1.045MHz
> > // Baud rate divider with 32768Hz XTAL @9600 = 32768Hz/9600 = 3.41
> > // //* An external watch crystal is required on XIN XOUT for ACLK *//
> > //
> > // MSP430F261x/241x
> > // -----------------
> > // /|\| XIN|-
> > // | | | 32kHz
> > // --|RST XOUT|-
> > // | |
> > // | P3.4/UCA0TXD|------------>
> > // | | 9600 - 8N1
> > // | P3.5/UCA0RXD|<------------
> > //
> > // B. Nisarga
> > // Texas Instruments Inc.
> > // September 2007
> > // Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version:
> > 3.42A
> > //******************************************************************************
> > #include "msp430x24x.h"
> > #include <signal.h>
> > #include <stdlib.h>
> >
> > void main(void)
> > {
> > WDTCTL = WDTPW + WDTHOLD; // Stop WDT
> > P3OUT &= ~(BIT4+BIT5);
> > P3SEL = 0x30; // P3.4,5 = USCI_A0 TXD/RXD
> > UCA0CTL1 |= UCSSEL_1; // CLK = ACLK
> > UCA0BR0 = 0x03; // 32kHz/9600 = 3.41
> > UCA0BR1 = 0x00; //
> > UCA0MCTL = UCBRS1 + UCBRS0; // Modulation UCBRSx = 3
> > UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state
> > machine**
> > IE2 |= UCA0RXIE; // Enable USCI_A0 RX
> > interrupt
> >
> > //eint();
> > //__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, interrupts
> > enabled
> > for(;;);
> > }
> >
> > // Echo back RXed character, confirm TX buffer is ready first
> > interrupt ( USCIAB0RX_VECTOR ) wakeup USCI0RX_ISR(void)
> > {
> > while (!(IFG2&UCA0TXIFG)); // USCI_A0 TX buffer ready?
> > UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
> > }
> >
> >
> >
> >
> > ------------------------------------------------------------------------------
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> > [email protected]
> > https://lists.sourceforge.net/lists/listinfo/mspgcc-users
> >
>
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