Thanks; I'd fixed the issue for UCA, but neglected to do the same for UCB, and wasn't using that header by the time I validated UCB functionality. I'll fix usci.h in my variant msp430-libc, but you may be better off using usci_5xx.h, which gives up on trying to support everything in one file, instead trying to match the TI headers in using consistent register names across modules. There are several other headers where there's a 5xx-specific version that should be preferred.
Peter On Mon, Mar 15, 2010 at 6:42 PM, Anthony Asterisk < [email protected]> wrote: > I found an error in the usci.h modification for the 5xxx series. The > definitions for UCBxCTL0/1 are swapped. The UCAxCTL are ok. > > Here are the versions of the file I'm using: > * 2009-11-20 - modifications by J.M.Gross <[email protected]> > * - split definitions for 8/11port and 2/4 USCI CPUs > * - added PMM module > * > * $Id: msp430x54xx.h,v 1.5 2009/06/04 21:55:18 cliechti Exp $ > > and > > * 2009-11-20 - modifications by J.M.Gross <[email protected]> > * - split definitions for 8/11port and 2/4 USCI CPUs > * - added PMM module > * > * $Id: msp430x54xx.h,v 1.5 2009/06/04 21:55:18 cliechti Exp $ > > > Here is an example of the definitions.... > > #define UCA0CTL0_ __MSP430_USCI5_BASE_0__ + 0x01 > // USCI control 0 (sic) > sfrb(UCA0CTL0, UCA0CTL0_); > #define UCA0CTL1_ __MSP430_USCI5_BASE_0__ + 0x00 > // USCI control 1 (sic) > sfrb(UCA0CTL1, UCA0CTL1_); > #define UCB0CTL0_ __MSP430_USCI5_BASE_0__ + 0x20 > // USCI synchronous control 0 > sfrb(UCB0CTL0, UCB0CTL0_); > #define UCB0CTL1_ __MSP430_USCI5_BASE_0__ + 0x21 > // USCI synchronous control 1 > sfrb(UCB0CTL1, UCB0CTL1_); > #define UCA1CTL0_ __MSP430_USCI5_BASE_1__ + 0x01 > // USCI control 0 (sic) > sfrb(UCA1CTL0, UCA1CTL0_); > #define UCA1CTL1_ __MSP430_USCI5_BASE_1__ + 0x00 > // USCI control 1 (sic) > sfrb(UCA1CTL1, UCA1CTL1_); > #define UCB1CTL0_ __MSP430_USCI5_BASE_1__ + 0x20 > // USCI synchronous control 0 > sfrb(UCB1CTL0, UCB1CTL0_); > #define UCB1CTL1_ __MSP430_USCI5_BASE_1__ + 0x21 > // USCI sync > > > Here is the complete patch: > > u...@instant-contiki:~/contiki-2.x/platform/castlerock/tools/msp430-gcc-4.4.3/msp430/include/msp430$ > diff -crB usci.h.orig usci.h > *** usci.h.orig 2010-03-15 21:34:58.000000000 -0400 > --- usci.h 2010-03-15 21:36:32.000000000 -0400 > *************** > *** 376,384 **** > #define UCA0IV_H_ __MSP430_USCI5_BASE_0__ + 0x1F > sfrb(UCA0IV_H, UCA0IV_H_); > > ! #define UCB0CTL0_ __MSP430_USCI5_BASE_0__ + 0x20 > // USCI synchronous control 0 > sfrb(UCB0CTL0, UCB0CTL0_); > ! #define UCB0CTL1_ __MSP430_USCI5_BASE_0__ + 0x21 > // USCI synchronous control 1 > sfrb(UCB0CTL1, UCB0CTL1_); > #define UCB0BR0_ __MSP430_USCI5_BASE_0__ + 0x26 > // USCI synchronous bit rate 0 > sfrb(UCB0BR0, UCB0BR0_); > --- 376,384 ---- > #define UCA0IV_H_ __MSP430_USCI5_BASE_0__ + 0x1F > sfrb(UCA0IV_H, UCA0IV_H_); > > ! #define UCB0CTL0_ __MSP430_USCI5_BASE_0__ + 0x21 > // USCI synchronous control 0 > sfrb(UCB0CTL0, UCB0CTL0_); > ! #define UCB0CTL1_ __MSP430_USCI5_BASE_0__ + 0x20 > // USCI synchronous control 1 > sfrb(UCB0CTL1, UCB0CTL1_); > #define UCB0BR0_ __MSP430_USCI5_BASE_0__ + 0x26 > // USCI synchronous bit rate 0 > sfrb(UCB0BR0, UCB0BR0_); > *************** > *** 450,458 **** > #define UCA1IV_H_ __MSP430_USCI5_BASE_1__ + 0x1F > sfrb(UCA1IV_H, UCA1IV_H_); > > ! #define UCB1CTL0_ __MSP430_USCI5_BASE_1__ + 0x20 > // USCI synchronous control 0 > sfrb(UCB1CTL0, UCB1CTL0_); > ! #define UCB1CTL1_ __MSP430_USCI5_BASE_1__ + 0x21 > // USCI synchronous control 1 > sfrb(UCB1CTL1, UCB1CTL1_); > #define UCB1BR0_ __MSP430_USCI5_BASE_1__ + 0x26 > // USCI synchronous bit rate 0 > sfrb(UCB1BR0, UCB1BR0_); > --- 450,458 ---- > #define UCA1IV_H_ __MSP430_USCI5_BASE_1__ + 0x1F > sfrb(UCA1IV_H, UCA1IV_H_); > > ! #define UCB1CTL0_ __MSP430_USCI5_BASE_1__ + 0x21 > // USCI synchronous control 0 > sfrb(UCB1CTL0, UCB1CTL0_); > ! #define UCB1CTL1_ __MSP430_USCI5_BASE_1__ + 0x20 > // USCI synchronous control 1 > sfrb(UCB1CTL1, UCB1CTL1_); > #define UCB1BR0_ __MSP430_USCI5_BASE_1__ + 0x26 > // USCI synchronous bit rate 0 > sfrb(UCB1BR0, UCB1BR0_); > *************** > *** 524,532 **** > #define UCA2IV_H_ __MSP430_USCI5_BASE_2__ + 0x1F > sfrb(UCA2IV_H, UCA2IV_H_); > > ! #define UCB2CTL0_ __MSP430_USCI5_BASE_2__ + 0x20 > // USCI synchronous control 0 > sfrb(UCB2CTL0, UCB2CTL0_); > ! #define UCB2CTL1_ __MSP430_USCI5_BASE_2__ + 0x21 > // USCI synchronous control 1 > sfrb(UCB2CTL1, UCB2CTL1_); > #define UCB2BR0_ __MSP430_USCI5_BASE_2__ + 0x26 > // USCI synchronous bit rate 0 > sfrb(UCB2BR0, UCB2BR0_); > --- 524,532 ---- > #define UCA2IV_H_ __MSP430_USCI5_BASE_2__ + 0x1F > sfrb(UCA2IV_H, UCA2IV_H_); > > ! #define UCB2CTL0_ __MSP430_USCI5_BASE_2__ + 0x21 > // USCI synchronous control 0 > sfrb(UCB2CTL0, UCB2CTL0_); > ! #define UCB2CTL1_ __MSP430_USCI5_BASE_2__ + 0x20 > // USCI synchronous control 1 > sfrb(UCB2CTL1, UCB2CTL1_); > #define UCB2BR0_ __MSP430_USCI5_BASE_2__ + 0x26 > // USCI synchronous bit rate 0 > sfrb(UCB2BR0, UCB2BR0_); > *************** > *** 598,606 **** > #define UCA3IV_H_ __MSP430_USCI5_BASE_3__ + 0x1F > sfrb(UCA3IV_H, UCA3IV_H_); > > ! #define UCB3CTL0_ __MSP430_USCI5_BASE_3__ + 0x20 > // USCI synchronous control 0 > sfrb(UCB3CTL0, UCB3CTL0_); > ! #define UCB3CTL1_ __MSP430_USCI5_BASE_3__ + 0x21 > // USCI synchronous control 1 > sfrb(UCB3CTL1, UCB3CTL1_); > #define UCB3BR0_ __MSP430_USCI5_BASE_3__ + 0x26 > // USCI synchronous bit rate 0 > sfrb(UCB3BR0, UCB3BR0_); > --- 598,606 ---- > #define UCA3IV_H_ __MSP430_USCI5_BASE_3__ + 0x1F > sfrb(UCA3IV_H, UCA3IV_H_); > > ! #define UCB3CTL0_ __MSP430_USCI5_BASE_3__ + 0x21 > // USCI synchronous control 0 > sfrb(UCB3CTL0, UCB3CTL0_); > ! #define UCB3CTL1_ __MSP430_USCI5_BASE_3__ + 0x20 > // USCI synchronous control 1 > sfrb(UCB3CTL1, UCB3CTL1_); > #define UCB3BR0_ __MSP430_USCI5_BASE_3__ + 0x26 > // USCI synchronous bit rate 0 > sfrb(UCB3BR0, UCB3BR0_); > >
