Hi!

You're right, there isn't a difference. Sometimes one should read the docs 
twice.
The datasheet lists the default interval to be 1s, yet this is correct only if 
you
set the clock source to 32768Hz. Which is the default for ACLK (LFXT1 or
REFO =32768Hz).
Unfortunately, SMCLK is set as the default clock, which is DCOCLK/2
like MCLK. 
So the timeout comes after 32768 MCLK cycles. Which is 32ms on the 5x
(with the clocks defaulting to 1MHz) and ~54ms on the 1x series with their
by default slower DCO.

I think this is a quirk in the docs and I will report it to the docs department.
It's not the first time they got something from me during the last year :)

I never noticed because I still use my own startup code which hasn't changed
since 1x, and which triggers the WDT.

So triggering the WDT in the copy loop is still necessary :(
Sorry for making this wrong statement. Sometimes even a 'guru' (title granted 
by TI)
can be wrong ;)

JMGross

----- Ursprüngliche Nachricht -----
Von: Peter Bigot
An: JMGross
Gesendet am: 15 Mrz 2011 12:25:41
Betreff: Re: [Mspgcc-users] Changes to mspgcc CRT capabilities in uniarch 
release

> Well, since the loop counters in the init code are word registers, there
> is only one 3-instruction-loop for each init stage (copy/clear).
> And running a complete loop may easily exceed default WDT timeout
> on 1x/2x/4x devices (only on 5x/6x the default WDT interval is long enough)

Can you provide references for this?  From what I read in the users
guides, both 1x and 5x/6x devices power-up with the WDT set at roughly
32msec.

Or is it "long enough" simply because the standard clock rate on the
5x/6x devices is higher?

Peter


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