----- Ursprüngliche Nachricht ----- Von: Przemek Klosowski An: Luis Rossi Gesendet am: 24 Mai 2011 22:34:17
> Now the original runtime interface in both versions was based on a > flawed model where lot of the MSP chip model-specific info (e.g. > differences in periphereal addresses, memory map, etc) was encoded in > the compiler. This became unsustainable as the model count balooned to > over 300, so MSP developers started shifting the chip dependent parts > to per-chip header files, provided by TI; > this is what is called 'uniarch'. It is of course based on the current > version of GCC, i.e. v.4. Leaves one question open: what happened to the device-specific workarounds for certain errata? Does the compiler now generate code that may hit the errata and work faulty on some processors? Or does the compiler always include the workarounds, leading to inefficient code on processors where the errata don't apply? Or does the translation from the processor type parameter to the uniarch parameters include a 'use workarounds x+y+z' setting? (haven't seen that mentioned before) ------------------------------------------------------------------------------ vRanger cuts backup time in half-while increasing security. With the market-leading solution for virtual backup and recovery, you get blazing-fast, flexible, and affordable data protection. Download your free trial now. http://p.sf.net/sfu/quest-d2dcopy1 _______________________________________________ Mspgcc-users mailing list Mspgcc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/mspgcc-users
