wow thanks
From cPhone On Aug 8, 2011, at 7:38 AM, "JMGross" <[email protected]> wrote: > Hi Eric, > > the 1.8V in the datasheet are worst-case value. It may well be thaat you can > significantly go above 8MHz with 1.8V. However, I recommend increasing the > capacitance on teh VCore pin. The main problem is that the > internal voltage regulator reaches its limit for the stable core voltage if > the input voltage is too low. > The core voltage is 1.4V(1.44V in LPM) when PMMCOREV is 0 (the default on > 5438A). On this voltage, operation up to 8MHz is guaranteed. If you exceed > 8MHz, this may mean that the flash or CPU needs more > than 1.4V for proper operation, it may also mean that the voltage regulator > cannot provide 1.4V anymore due to the higher current comsumption. Or both. > But it can also be none of them. 400kHz are almost 5%. > It may or may not work, I really cannot say. It probably will work with most > MSPs but perhaps won't with some. > > However, you're asking about DCO and FLL. And that's another thing to > consider. > The DCO most likely cannot provide 8MiHz. > In fact, the DCO can only provide 256 different frequencies in the range of > 70kHz and 135MHz. > It is not likely that 8MiHz is one of them. (or 8Mhz). > So the DCO uses modulation patterns to switch between two frequencies. A > higher one and a lower one, to give 30 more different 'average' frequencies > between the 256 'real' ones. > But this also means that the DCO will e.g. switch between 8MHz and 9MHz to > give your requested 8MiHz. So the cpu is clocked with 9MHz for some clock > cycles. > (to get the worst case upper frequency and maximum error, you have to do lots > of math on the DCO frequency table, checking min/max frequencies and DCO tap > ratio etc.) > Some time ago I calculated that worst case you may only use 23.7MHz on an > MSP430F5438A, so you can be sure that the DCO will never go above 25MHz on > any individual MSP. > > The FLL is quite good. It increases and decreases DCO tap and modulation > setting so it gets n DCO ticks per each reference tick. With my 5438s I > didn't have problems with 115200Bd connections using the FLL for > a 16MHz DCO clock. With the internal REFO as reference. > Since the maximum clock for the 5438 is 18MHz, I'm on the safe side :) > > However, there are some more things to keep in mind: > 1) the FLL does not change the RSEL setting. So you must still select the > proper RSEL range. > 2) the crystal must be up and running before you can activate the FLL, otr > the FLL will try to adjust the DCO to x*0Hz = 0Hz. you can use the internal > REFO instead, ot let the FLL start on REFO until the crystal is > running, and switch its reference then (to save some time). > 3) you don't know when the frequency has settled. The DCOFFG bit is cleared > as soon as the DCOx bits have been adjusted to >0 and are still <31. If > DCOFFG can be cleared, this only means that the DCO is not > adjusted against its limits. It does NOT mean that it has reached the final > value. > All you can do is checking the changes and noticing if the change changes > direction. So the FLL is no longer increasing MODx and DCOx but swings > between two settings instead. > you can speedup the process by detecing a safe (too low for sure) but non-0 > start value for DCOx. Based on experience. It shortens the adjustment time, > since the FLL only adjusts one step at a time, so it takes > worst case 1024 reference ticks to reach the final position (32 DCOx and 32 > MODx settings). > > The FLL will take care of any required recalibration due to temperature drift. > However, you cannot rely on this if you enter an LPM that switches the FLL or > the DCO or the reference off. In case the FLL is switched off, it is NOT > switched on during ISR execution. But disabling reference or > DCO will cause the FLL (if sitll enabled) to try to adjust the DCO up or down > during LPM. > So you should explicitely disable the FLL before entering any LPM except > LPM0, and only re-enable it if you remain in active mode for more than 2 or 3 > reference ticks. > > JMGross > > > ----- Ursprüngliche Nachricht ----- > Von: Eric Decker > An: JMGross > Gesendet am: 07 Aug 2011 07:22:53 > Betreff: Questions about 5438 FLL and DCO > > Hi Jens, > > I have a few questions that I hope you can answer. > > We are using a 5438a (msp430f5438a) ti cpu. We are running it at 1.8V and > the docs say the max system frequency (dcoclk) is 8MHz (8,000,000). > > How risky is it to run the DCOCLK at 8,388,608 Hz (8MiHz, binary megahertz) > while staying at Vcore of 1.8V? > > > > Also how good is the FLL? > > On previous processors, 1611 and 2618 we had to periodically mess with > calibrating the DCO to ACLK (off 32768 Xtal) by tweaking various DCO > parameters. If using the FLL I assume that we don't have to do that > anymore. That it just works. Is that a reasonable assumption? > > > thanks, > > eric > > -- > Eric B. Decker > Senior (over 50 :-) Researcher > > ------------------------------------------------------------------------------ BlackBerry® DevCon Americas, Oct. 18-20, San Francisco, CA The must-attend event for mobile developers. Connect with experts. Get tools for creating Super Apps. See the latest technologies. Sessions, hands-on labs, demos & much more. Register early & save! http://p.sf.net/sfu/rim-blackberry-1 _______________________________________________ Mspgcc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/mspgcc-users
