----- Ursprüngliche Nachricht -----
Von: Sergey A. Borshch
Gesendet am: 09 Aug 2011 08:02:50
>inline void flash::Erase(address_t page)
>{
> asm volatile( "\r\n"
> " push %B0 \r\n"
> " push %A0 \r\n"
> " popx.a %A0 \r\n"
An interrupt happening here will clear the upper 4 bit of the page register.
On systems where the ISRs save 20 bit registers (far data model),
this kind of read/write is usually not necessary,as pointers are 20
bit anyway then.
Also, an interrupt during the erase will fetch 0x3FFF as ISR address,
crashing the system.
So SR should be saved, GIE cleared, and after the write, SR needs to be
restored.
Same applies to the read and write functions (except for the crash
situation which doesn't apply for reads)
> " mov %3, %2 \r\n" // FCTL1 = FWKEY | ERASE;
> " clrx 0(%A0) \r\n"
> :"=r"(page)
> :"0"(page), "m"(FCTL1), "i"((uint16_t)FWKEY | ERASE)
> );
>}
JMGross
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