On Fri, Dec 9, 2011 at 8:49 AM, JMGross <msp...@grossibaer.de> wrote: >>I am informed that silicon subject to erratum CPU18 is vulnerable to >>having the instruction following LPM flag sets be executed before LPM >>is entered, and that the CCS compiler will generate a NOP after BIS SR >>to compensate. The chips that are listed in the msp430mcu devices >>table as having this bug are the F54xx non-A versions (e.g., >>MSP430F5438, but not MSP430F5438A), and most of the CC430 chips. > > _executed_ is a different thing. The instruction is fetched (and a breakpoint > on it is triggered) on every MSP. > However, the instruction will be _executed_ the moment an interrupt is > triggered and LMP ends. However, it will be executed before the ISR > is entered, and not, as one would expect, after the ISR has ended LPM.
I could believe this, but please provide a reference supporting your claim. Peter ------------------------------------------------------------------------------ Cloud Services Checklist: Pricing and Packaging Optimization This white paper is intended to serve as a reference, checklist and point of discussion for anyone considering optimizing the pricing and packaging model of a cloud services business. Read Now! http://www.accelacomm.com/jaw/sfnl/114/51491232/ _______________________________________________ Mspgcc-users mailing list Mspgcc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/mspgcc-users
