On 2012-08-24, Grant Edwards <grant.b.edwa...@gmail.com> wrote: > On many processors doing things like clearing an interrupt flag is > done by writing a 1 to the bit you wish to clear. That makes the > hardware implementation much simpler and it lets you use a C statement > like: > > P1IFG = P1_PWR_SW; > > Which is much less likely to be a non-atomic operation.
I've always been a bit baffled why TI didn't follow the normal "write 1's to clear interrupt flags" paradigm. Instead, they chose something that's more complex for both software and hardware. IIRC, some of the early processors had bugs in the "special case" handling for the BIC instruction, and clearing interupt flags in some registers _didn't_ work reliably. -- Grant Edwards grant.b.edwards Yow! JAPAN is a WONDERFUL at planet -- I wonder if we'll gmail.com ever reach their level of COMPARATIVE SHOPPING ... ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ Mspgcc-users mailing list Mspgcc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/mspgcc-users