TO: Tomas Karlsson.
CC: [EMAIL PROTECTED]
There's valuable Spectravideo/MSX info on Tomas Karlsson's
Web pages:
http://home1.swipnet.se/~w-16418/right.htm
(This message is best seen with Courier New font, or other fixed-
width font, so that the diagrams appear as they should.)
Here are some replies to a couple of MSX and SV subjects...
TK>The centronics interface for SV starts at I/O port address
>10H, but the MSX is reserved up to 3FH.
I'm looking at the following document...
"MSX Technical Data Book: Hardware/Software Specifications."
Copyright (c) 1984 Microsoft Corporation.
Produced by ASCII Corporation.
Printed in Japan.
That book may be regarded as the original MSX "Bible" that
manufacturers would have designed their systems to. (I have
an aging loose 340-page 3-ring binder photocopy that's just
legible enough to read, but wouldn't photocopy or scan well.)
About I/O expansion, it says this...
"The MSX system specifications define the system device
I/O address space to be addresses from 40 to FF. The
addresses below 3F are left free. While other devices may
use this address space, other manufacturers may use the same
addresses for other purposes. Thus, we recommend that memory
addresses be used instead of I/O area. In later MSX versions,
it is possible that standard devices will use the unassigned
(reserved) addresses."
In more than one place, it advises that devices be mapped into
memory space, rather than I/O space, to avoid duplicate address
conflicts by way of the slot select/control.
In the MSX Hardware Specifications section, the following I/O
Address Map overview is given (the unassigned are Reserved) ...
FF +------------------------------+
| |
F8 +------------------------------+
F7 | Audio/Video Control |
+------------------------------+
| |
F0 +------------------------------+
| |
E0 +------------------------------+
| ROM for Chinese Characters |
D8 +------------------------------+
| Floppy Disk Controller |
D0 +------------------------------+
| |
C0 +------------------------------+
| Light-pen interface |
B8 +------------------------------+
| |
B5 +------------------------------+
| Calendar Clock |
B4 +------------------------------+
| External Memory |
B0 +------------------------------+
| PPI (8255) |
A8 +------------------------------+
| PSG (AY-3-8910) |
A0 +------------------------------+
| VDP (9918A) |
98 +------------------------------+
| Printer Interface |
90 +------------------------------+
| |
88 +------------------------------+
| RS-232C Serial Interface |
80 +------------------------------+
| Reserved |
| |
40 +------------------------------+
| Unspecified |
| (available for applications) |
00 +------------------------------+
The specific I/O addresses for each device are covered in the
sections of the MSX-TDB (MSX Technical Data Book) which detail
the device/interface implementation.
BTW, the UART in the MSX Specification is an Intel 8251. An 8253
counter/timer circuit (CTC) chip is also specified, to provide
software-programmable baud rates, because the 8251 UART doesn't
have an internal baud-rate generator.
The RS-232C Serial Interface I/O address specification is...
80H R/W 8251 Data Port
81H R/W 8251 Command/Status Port
82H R Status Sense Port: CTS, CTC Channel-2, RI, & CD.
82H W Interrupt Mask Register
83H Reserved
84H R/W 8253 Counter 0
85H R/W 8253 Counter 1
86H R/W 8253 Counter 2
87H W 8253 Mode Register
I/O address 82H is bit-mapped...
+----+------------------------------------+
|Bit | Description |
+----+------------------------------------+
| D7 | CTS (Clear To Send) |
| | 0: Asserted |
| | 1: Negated |
| D6 | Timer/Counter Output-2 from i8253. |
| D5 | --+ |
| D4 | | Reserved |
| D3 | | |
| D2 | --+ |
| D1 | * RI (Ring Indicator) |
| | 0: Asserted |
| | 1: Negated |
| D0 | * CD (Carrier Detect) |
| | 0: Asserted |
| | 1: Negated |
+-----------------------------------------+
Signals above with the asterisk (*) are optional. If
only one of those signals is chosen, it must be CD.
I/O address 83H is also bit-mapped...
+----+------------------------------------------+
|Bit | Description |
+----+------------------------------------------+
| D7 | --+ |
| D6 | | Reserved |
| D5 | | |
| D4 | --+ |
| D3 | * Timer Interrupt from i8253 channel 2 |
| | 1: Mask Interrupt (Initial value) |
| | 0: Enable Interrupt |
| D2 | * Sync Character detect/Break detect |
| | 1: Mask Interrupt (Initial value |
| | 0: Enable Interrupt |
| D1 | * Transmit Data Ready (Tx Ready) |
| | 1: Mask Interrupt (Initial value) |
| | 0: Enable Interrupt |
| D0 | Receive Data Ready (Rx Ready) |
| | 1: Mask Interrupt (Initial value) |
| | 0: Enable Interrupt |
+-----------------------------------------------+
Signals above with an asterisk (*) are optional. The
minimum requirement for the interrupts is thus Rx Ready.
The 8253 CTC has a 1.8432 MHz crystal input, which allows baud
rates of from 50 to 19200 bps. CTC Channel-0 provides the Rx
baud rate; CTC Channel-1 provides the Tx baud rate; CTC Channel-
2 is used by applications (interrupt generated optionally).
The CTC Channel scale-factor (SF) for specific Rx/Tx rates (BPS)
may be calculated as follows ...
SF = 1843200 / (BPS * 16)
See the 8253 CTC technical data sheets for programming details.
Now let's switch to info relevant to Spectravideo system users...
TK>Talking of cartridges, you wouldn't happen to know why there
>are 4 chips select signals in the cartridge port when there are
>only 2 cartridge banks. Are they mapped to other locations than
>0H and 8000H?
You're referring to CCS1 (pin 27), CCS2 (pin 28), CCS3 (pin 25),
and CCS4 (pin 26) of the SpectraVideo SV-318/328 cartridge slot?
Well, it's time for some back-engineering ...
First off, I believe the SV schematics are wrong; the CCSx are
active-low signals -- because a 74LS139 IC is used -- so I'll
refer to them as ~CCS1, ~CCS2, ~CCS3 and ~CCS4.
The ~CCSx decode logic has the following signal dependencies...
~CCS1 ---+
|---- ~BK21 ----------+
~CCS2 ---+ |
| ~CART, ~MREQ, A15, A14.
~CCS3 ------ ~ROMEN0 --+ |
|-------+
~CCS4 ------ ~ROMEN1 --+
The ~CART, ~ROMEN0, ~ROMEN1, and ~BK21 signals are set or
cleared by writing to the bit-mapped PSG Port B ...
~CART PSG Port B, bit-0..
~BK21 PSG Port B, bit 1.
~ROMEN0 PSG Port B, bit-6.
~ROMEN1 PSG Port B, bit-7.
Both ~CART and ~MREQ must be low for any ~CCSx to be selected.
In addition to ~CART and ~MREQ, ~CCS3 requires~ROMEN0 to be low.
In addition to ~CART and ~MREQ, ~CCS4 requires~ROMEN1 to be low.
Address lines A0..A13 within the cartridge slot can address 16k
of memory space. Let's regard each of the four ~CCSx as being a
select for one 16k-bank of memory. Address lines A15 and A14 are
then used to select any one of those four 16k-banks. This places
the cartridge slots into the following memory-map segments ...
~CCS1: SV memory addresses 0000H..3FFFH (16k) (A15:0, A14:0)
~CCS2: SV memory addresses 4000H..7FFFH (16k) (A15:0, A14:1)
~CCS3: SV memory addresses 8000H..BFFFH (16k) (A15:1, A14:0)
~CCS4: SV memory addresses C000H..FFFFH (16k) (A15:1, A14:1)
For use of either ~CCS1 or ~CCS2 cartridges, which conflict with
the on-board SV ROM code at addresses 0000H..7FFFH, the software
application must first disable the ROM by setting ~BK21 low. If
this isn't done, both the ROM and cartridge will respond to
accesses into their mutual address -- the result will be garbage
data, at the very least, and possibly damage to TTL logic chips.
Also, before disabling the ROM, your code should disable the Z80
interrupts, because each interrupt causes the Z80 to call address
0038H. So, your code should do its business as quickly as possible,
then re-enable the ROM, and then re-enable Z80 interrupts so that
it may continue with its interrupt-based "house-keeping" activities.
Because cartridges doesn't have Read, Write, or bus-direction
signals, the cartridge memory/device logic must determine whether
it should read the Z80 data lines, or load the data lines. This
can be done with memory-mapped I/O, with some address ranges being
read-only and some as write-only in the cartridge's 16k space.
Regards,
Greg Vigneault
(Note that my real e-mail address is as below, not as it may
appear in the above "From" field -- for anti-spam reasons.)
[EMAIL PROTECTED]
Wednesday, August 12, 1998. Toronto, Ontario, Canada.
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