Hi,


Who know about MSX-hardware mail list?. If such be
There is in view of hardware development.

It is Correct have on slot-connector the pins /TREFA,/TREFC,/TREFR ?

/TREFA Timing Reference A (output, active Low, tri-state).
This timing reference signal goes Low at the end of T2 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used to
control the address multiplexer for a DRAM interface or as
the /RAS signal at higher processor clock rates.

/TREFC Timing Reference C (output, active Low, tri-state).
This timing reference signal goes Low at the end of T3 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used as the
/CAS signal for DRAM accesses.

/TREFR Timing Reference R (output, active Low, tri-state).
This timing reference signal goes Low at the end of T1 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used as the
/RAS signal for DRAM accesses.

Wanted their use. But in the mode DMA affiliated charge must their form.
This complicates its contents.

/UMCS Upper Memory Chip Select (output, active Low, tri-state).
This signal is activated during a memory read,
memory write, or optionally a refresh transaction when
accessing the highest portion of the linear address space
within the first 16 Mbytes, but only if this chip select
function is enabled.

/LMCS Low Memory Chip Select (output, active Low, tri-state).
This signal is activated during a memory read or
memory write transaction when accessing the lower por-tion
of the linear address space within the first 16 Mbytes,
but only if this chip select function is enabled.

/MCS3-/MCS0 Mid-range Memory Chip Selects (output,
active Low, tri-state). These signals are individually active
during memory read or write transactions when accessing
the mid-range portions of the linear address space within the
first 16 Mbytes. These signals can be individually enabled
or disabled.

Too the most. Why Zilog did not do a possibility of shaping these signals in
DMA mode.
Z380 in mode of seizure of buses could read address and form signals /XMCSX
:)

Bye
Valery




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