For the historians: A little history on the Z-x80 family of Zilog
from: Great Microprocessors of past and present,
http://www.cs.uregina.ca/~bayko/cpu.html
"Part IV: The Zilog Z-80 - End of an 8-bit line (July 1976) . . . .
The Z-80 was intended to be an improved 8080 (designed by ex-Intel engineers), and
it was vastly improved. It also used 8 bit data and 16 bit addressing, and could
execute all of the 8080 (but not 8085) op codes, but included 80 more,
instructions (1, 4, 8 and 16 bit operations and even block move and block I/O).
The register set was doubled, with two banks of data registers (including A and F)
that could be switched between. This allowed fast operating system or interrupt
context switches. The Z-80 also added two index registers (IX and IY) and 2 types
of relocatable vectored interrupts (direct or via the 8-bit I register).
Clock speeds ranged from the original Z-80 2.5MHz to the Z80-H (later called
Z80-C) at 8 MHz, and later a CMOS version at 10MHz.
Like many processors (including the 8085), the Z-80 featured many undocumented
instructions. In some cases, they were a by-product of early designs (which did
not trap invalid op codes, but tried to interpret them as best they could), and in
other
cases chip area near the edge was used for added instructions, but fabrication
made the failure rate high. Instructions that often failed were just not
documented, increasing chip yield. Later fabrication made these more reliable.
But the thing that really made the Z-80 popular in designs was the memory
interface - the CPU generated its own RAM refresh signals, which meant easier
design and lower system cost, the deciding factor in its selection for the TRS-80
Model 1. That and its 8080 compatibility, and CP/M, the first standard
microprocessor operating system, made it the first choice of many systems.
Embedded varients of the Z-80 were also produced. Hitachi produced the 64180
(1984) with added components (two 16 bit timers, two DMA controllers, three serial
ports, and a segmented MMU mapping a 20 bit (1M) address space to any three
variable sized segments in the 16 bit (64K) Z-80 memory map), a design Zilog and
Hitachi later refined to produce the Z-180 and HD64180Z (1987?) which were
compatible with Z-80 peripheral chips, plus variants (Z-181, Z-182). The Z-280 was
a 16 bit version introduced about July, 1987 (loosely based on the ill-fated
Z-800), with a paged (like Z-180) 24 bit (16M) MMU (8 or 16 bit bus resizing),
user/supervisor modes and features for multitasking, a 256 byte (4-way) cache, 4
channel DMA, and a huge number of new op codes tacked on (total of almost 3,500,
including previously undocumented Z-80 instructions), though the size
made some very slow. Internal clock could be run at twice the external clock (ex.
16MHz CPU with a 8MHz bus), and additional on-chip components were available. A
16/32 bit Z-380 version also exists (1994) with added 32-bit linear addressing
mode (not Z-80 compatible).
"
GreetZ,
Jacco Bot
Antoni Burguera wrote:
> >>AFAIK, Zilog has stopped producing the z380 :-(
> >
> > Any ideas to substitute Z380?
> >
> > Z382?
>
> Zilog has stopped? But I have read that Z380 is very used in military
> applications...
>
****
MSX Mailinglist. To unsubscribe, send an email to [EMAIL PROTECTED] and put
in the body (not subject) "unsubscribe msx [EMAIL PROTECTED]" (without the
quotes :-) Problems? contact [EMAIL PROTECTED] (www.stack.nl/~wiebe/mailinglist/)
****
