On Fri, 19 Mar 1999 [EMAIL PROTECTED] wrote:
> >Marco Antonio Simon dal Poz <[EMAIL PROTECTED]> wrote:
> >>Maarten ter Huurne wrote:
> >>Do you know a FDC that supports 1.2Mb and 1.44Mb drives and is still being
> >>produced, and have good documentation?
>
> I think these docs and ICs are unavailable today.
Too bad! Well, if someone still have the detailed documentation, we still
can implement in a FPGA! I think that almost an entire MSX can be
implemented in a FPGA.
> >>Note that 3.5MHz is too slow to allow reading of 1.44MB disks. The "inner
> >>loop" of the sector read routine is too slow to cope with the data flow.
>
> Drivers 1.44MB uses 360 r.p.m. when 720kb uses 300 r.p.m. ?
No, 5.25" 1.2Mb runs at 360rpm. All the others run at 300rpm. This explain
why a 360kb disk has a higher transfer rate in a 1.2Mb drive.
> >> So
> >>if you want to create 1.44MB drives for MSX, you either have to use 7MHz
> >>Z80 or use some kind of buffer for reading sectors.
>
> >Are you sure? A 720kb disk works with a FDC that handles 250kbits/s, a
> >1440kb disk works with a FDC that handles 500kbits/s.
>
> I don't know, but if angular speed is 360 * 2 * PI / 60 ,
> that required more CPU speed OR _DMA_ for flow control.
If the DMA works at 3.57MHz, there's no advantage in it.
> >This means that the
> >main routine should be able to read 12500 bytes per turn. It means that
> >this routine should run 12500 times in 0.2 seconds. Then, the routine
> >should spend a maximum of 16 microseconds. In a 3.57561149MHz, this means
> >57 clockcicles.
>
> If I used a trigger for control signal "data available" on
> hardware (i.e. waiting for "Wait" signal comes up), avoid
> you routine ?
No! You'll need a buffer (or a FIFO).
> I see possibilities. Control is set on read on D0h port.
I see possibilities, and all of them include a small internal RAM.
> Only for information, the correct number of states (T):
>
> TOTAL 11+4+12+4+5+16+10 = 62 T-cicles if no-wait inserted.
>
> If wait-logic is used, the read routine is:
>
> LD HL, address 10T
> LD C, D3h 7T
> LOOP:IN A, (D0h) 11T <- WAIT INSERTED (Hardware tests
> RRCA 4T data bus D7 )
What happened with JR NC,LOOP ?
> RRCA 4T
> RET NC 5T
> INI 16T
> JP LOOP 10T
>
> TOTAL 11+4+4+5+16+10 = 50 T-cicles + waits.
>
> I try to work on this scheme, but I need 1.44M FDC IC.
> Who know this IC commercial number ?
Intel 82077AA, but it's not still produced. There are others, but I don't
know them.
Greetings from Brazil!
-----------------------------------------------------------------
Marco Antonio Simon Dal Poz http://www.lsi.usp.br/~mdalpoz
[EMAIL PROTECTED] "Apple" (c) Copyright 1767, Sir Isaac Newton
/"\
\ / CAMPANHA DA FITA ASCII - CONTRA MAIL HTML
X ASCII RIBBON CAMPAIGN - AGAINST HTML MAIL
/ \
****
MSX Mailinglist. To unsubscribe, send an email to [EMAIL PROTECTED] and put
in the body (not subject) "unsubscribe msx [EMAIL PROTECTED]" (without the
quotes :-) Problems? contact [EMAIL PROTECTED] (www.stack.nl/~wiebe/mailinglist/)
****
