On Sat, 23 Sep 2000, you wrote:
> *** About the horizontal interrupt
>
> All relevant definitions on a row:
> -FH: Bit 0 of status register 1
> -IE1: Bit 4 of mode register 0
> -IL: Line number in mode register 19
> -DL: The line that the VDP is going to display (corrected for vertical
> scroll) -IRQ: Interrupt request line of VDP to Z80
>
> At the *start* of every new line (display, bottom border, part of vertical
> display), the VDP does:
> -FH = (FH && IE1) || (IL==DL)
FH can be 1 for 2 or 3 reads on a row: "start of line" is an interval, not a
single point in time.
> After reading of status register 1 by the CPU, the VDP does:
> -FH = 0
>
> Furthermore, the following is true all the time:
> -IRQ = FH && IE1
>
> The resulting behaviour:
> When IE1=0:
> -FH will be set as soon as display of line IL starts
> -FH will be reset as soon as status register 1 is read
> -FH will be reset as soon as the next display line is reached
>
> When IE=1:
> -FH and IRQ will be set as soon as display line IL is reached
> -FH and IRQ will be reset as soon as status register 1 is read
>
> Another subtile result:
> If, while FH and IRQ are set, IE1 gets reset, the next happens:
> -IRQ is reset immediately (since IRQ is always FH && IE1)
> -FH will be reset as soon as display of the next line starts (unless the
> next line is line IL)
David's trick depends on the fact that FH is reset immediately when IE1 is
reset, not at the start of the next line. David resets IE1 and then sets IE1.
If FH would be reset at the next line, an interrupt would be generated.
Anyway, I'll program the following test tonight:
1. set line interrupt to line 100 (any line is OK)
2. enable line interrupt (IE1:=1)
In the interrupt handler:
3. poll until start of line (using HR)
4. disable line interrupt (IE1:=0)
5. read FH (status register 1)
Step 4 and 5 are short enough to occur within a single display line. So if my
model is right, FH will be 0, if your model is right, FH will be 1.
Is this test scenario OK?
> *** About the vertical interrupt:
> Another relevant definition:
> -FV: Bit 7 of status register 0
> -IE0: Bit 5 of mode register 1
>
> I only know for sure the behaviour when IE0=1:
> -FV and IRQ will be set as soon as VR changes from 0 to 1
> -FV and IRQ will be reset as soon as status register 0 is read
>
> A consequence is that NO vertical interrupts will be generated during the
> overscan trick, described in the VR section above.
fMSX does a lot of event handling (keyboard, mouse etc) at the vertical
interrupt. In Unknown Reality it's impossible to quit fMSX or access the
debugger during the overscan part ;)
Bye,
Maarten
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