Looking inside the CX5M, I noticed that it has a rather curious
arrangement of DRAM. There are 8 4116 chips for the 16K of VRAM attached
to the TMS video chip and 4 41416 chips for the 32K of main memory. This
is curious because these are two different 16K technologies, one 1 bit
wide and the other 4 bits. Why use both in a design? Surely 6 41416 chips
would have been cheaper?
Perhaps it has something to do with refreshing. Maybe the TMS can't
refresh 8 row addresses that the 41416s require, whereas the main circuit
can. In that case, it ought to be quite easy to replace those 16K x 4
DRAMs with some 41464 64K x 4 chips, and play around with the slot select
signals a bit to get 128K in the CX5M. Has this been done before and been
documented somewhere on the net?
Richard
--
For info, see http://www.stack.nl/~wynke/MSX/listinfo.html
