I looked at this issue again today without understanding how to fix this. One thing is clearly odd : U27 (74LS139 used to generate the chip enable for the D2 and D3 ports) demonstrates a significant delay between O2/O3 ouputs and the E input. in particular, the D2 enable glitch happens even after the E is back high. I tried to replace the chip suspecting it may be faulty, with no success. May be I should try using a F or a HC ? I checked the contacts, solders, etc If the timing was so sensitive, I guess some other folks here would have experienced the same issue. but the board seems to work reliably for the group members. Or maybe no one is using the latch mode (P39 unused) ?
your thoughts will be very welcome thanks Philippe -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
