Meanwhile Dave you could try slapping a 47pF cap on the gate output pin. Might work
John From: [email protected] [mailto:[email protected]] On Behalf Of David Fry Sent: Friday, January 16, 2015 10:29 AM To: [email protected] Cc: [email protected] Subject: Re: [N8VEM-S100:6032] S-100 80386 CPU Board V03 - Master/Slave Switch Timing Problem ?? Hi John, Sure, I've placed an order today for a NOS 74L30 from an Ebay seller in Germany. Once I've retested with the slower device then I'll give an update/ possible temporary fix and draft a paragraph for the bugs section of the page. If that doesn't work then I'll get my soldering iron out and start building up my SMB PCB. once the 80386 GAL version is sorted, can put me down for one. regards David Fry On Friday, January 16, 2015 at 5:59:41 PM UTC, monahanz wrote: Hi David, I’ve kind of come to the same conclusion on this bit/port swapping circuit. Even though I never had a problem with it here I think there is potential for a race condition. I’m currently doing the 80486 board and have this whole circuit in one GAL. I’m attaching schematic FYI. I am currently doing an equivalent 80386 to work out bugs with GAL’s. On my second 80386 right now. My suggestion Dave is to bypass that onboard master/slave swapping problem and use the V2 SMB using the output of a bit to a port (rather that sINP+pDBIN). That at least for me, has always been reliable. Dave, when you get a chance could you write up a short paragraph so I can add it to the “bugs” section at the bottom of the S100Computers.com 80386 web page. Essentially splicing your recent postings into one paragraph John From: [email protected] <javascript:> [mailto:[email protected] <javascript:> ] On Behalf Of David Fry Sent: Friday, January 16, 2015 1:38 AM To: [email protected] <javascript:> Subject: [N8VEM-S100:6028] S-100 80386 CPU Board V03 - Master/Slave Switch Timing Problem ?? Hi John, I seen to have run into an issue with the recently released 80386 board involving the above subject. My hardware is:- S-100 Computers Propeller Console S-100 Computers 16MB SRAM V3 S-100 Computers MS-DOS Board V2 S-100 Computers Z80 Master CPU Board S-100 Computers 80386 CPU Board V03 (configured as slave) S-100 Computers ZFDC S-100 Computers CF/IDE Board V2 10 slot active terminated backplane The situation is, I can bring up the above system to Z80 monitor and press 'O' or 'W' to transfer control to the 80386 monitor, Then from within the 80386 monitor I can press 'Z' to transfer control back to the Z80 monitor, I could do this all day long and it works reliably. The issue is that when I am in the 80386 monitor (real mode) if I press the 'N' key to enter the IDE menu the 80386 CPU card drops out of control and hands back control to the Z80 monitor. I have spend a few hours looking into this and found that when the 'N' menu item is pressed the 'D' type flip flop U91A is falsely triggered providing the initiation of transfer back to the Z80 monitor. If when the 80386 card is active I remove jumper P67 1-2 allowing U52C to float high then I can enter menu item 'N' and access the IDE menu fine, obviously I can not then transfer back to the Z80 without replacing the link. I compared this part of the circuit with that of the 80286 board which works perfectly in my system running either it's on board 80286 Eproms or the 80386 Eprom code on the MS-DOS board. Both boards in essence use the same circuit to handle the port EDH switchover function but I did notice that on the 286 the address lines are buffered, on the 386 they are not. To cut a long story short I have substituted, a 74F00 into position U52 and replaced U55 with a 74LS244 as suggested in your listing, this has helped the situation and I can now get to the IDE menu 50% of the time, so it would seem to me that some spurious/possible timing condition is occurring causing the false trigger. Changing the 80386 CPU clock frequency doesn't help, I have tried 40Mhz, 30 Mhz & 16MHz clocks, all IC's on the board are new Texas Instruments parts. I have not yet build the SMB board yet so I rely on the on board port EDH circuit for bus handover. I also do not yet own a logic analyser,, would it be possible for you confirm if the timing is 'that' tight around this part of the circuit, and can you reproduce the problem in a system without a SMB board ?? many thanks in anticipation David Fry -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected] <javascript:> . For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
