David, I went through the posts - good analysis. I only have used MYIDE as a CP/M transient. The board I/O code in my system is burned in my system ROM just as my prior ST506 code was since there is not room in the ROM for both sets of code. I boot my system from a 1.2 MB 5.25 inch floppy.
I got bold a few minutes ago and removed the pull up SIP and replaced the 74S03's with 74LS00's. No instant cure but in looking at the sectors on the CF card I think things are better but no eureka. It did not degrade performance. I also will replace those two 74LS00's with 74ALS00's to further reduce the loading. Also U18 has pins 1 & 2 being driven by one 8255 line and the same for pins 4 & 5. I will lift one of each of those pairs and tie it to Vcc. Next step I will try is to remove the ICs driving the hex displays and LEDs. They are all LS TTL and put a somewhat higher load on the 8255 lines than do the CF cards themselves. I will pull U10, U12, U13, and U14. I will no longer have the benefit of the hex displays and the LEDs but to be honest they are not that useful when the board is in my system as I really can not see them and I do not trust observations when a board is on an extender. One final note - I have been staring at the MYIDE code and at my ROM code that was mostly a copy of the MYIDE code. At least one place in the code (both sets) has me looking at adding a busy check. I don't want to make too much of that right now as I may just be grasping at straws. I have only a little time today - more tomorrow. I will report results. Rich Leary On Saturday, January 17, 2015 at 2:44:34 AM UTC-7, David Fry wrote: > Hi Rich, > > I was the person who originally proposed the changing of the 680 ohm > resistor sil to 330 ohm based upon my own personal findings, the upgrade to > the 74S03 was necessary to cope with the increased current. At the time of > this mod I was thinking that this was crazy, it shouldn't take this kind of > brute force to drive a low power card but I can only report what my > oscilloscope was telling me, the CF card R/W lines were loading down the > driving gate, ejecting the card gave me full TTL levels.!!! > As you say, if the CF card input leakage current is 1uA then it shouldn't > load the driving gate at all :-) > > Having made the mod (and it's the only one !) my card has been reading and > writing to CF cards for about a year now. I almost exclusively use the > Kingston 4GB card with the white flower on. > > One thought that has crossed my mind was a subsequent post I later made on > corrupted CF writes to the directory area of the CF card, take a look at > the post below and start reading from date 6/25/14 (it's a long post) to > see if the resolution has any relevance to your symptoms. > > > https://groups.google.com/forum/?fromgroups#!searchin/n8vem-s100/memtop/n8vem-s100/iuHcpanZwq4/VAmvr6Q_O_MJ > > regards > > David Fry > > On Saturday, January 17, 2015 at 5:14:42 AM UTC, Rich Leary wrote: > >> John, >> >> It is puzzling. I am using all 74LS except the two 74S03s and have tried >> both NMOS and CMOS varieties of the 8255. >> >> I have gone back to the CF and IDE specs and looked hard at the signal >> level specifications. My preliminary look seems to conflict with the build >> notes. >> >> The CF spec defines three type of signals at the interface and one of >> them (Type 1) does specify a 4V Vih for some signals. Other signals use >> either 2.0V or 2.8V. >> >> What is confusing is that the Type 1 signals are the address lines (An) >> and the data lines (Dn). The IORD, IOWR, and CSn (chip select n) lines are >> all Type 3 and the card inputs for those lines only require Vih of 2.8V to >> trigger the Schmitt Trigger that Type 3 uses. But the IORD, IOWR, and >> CSn lines are what are driven by the 74S03 or 74H03 ICs on the S100 board. >> RESET is a Type 2 signal and Vih need only be 2.0V. >> >> The only on-board pull ups are those associated with the 74S03 or 74H03 >> ICs and they are very low value. The schematic shows 680 ohm but the notes >> suggest something like 330. >> >> What is also important to note is that the CF card input leakage current >> is very low at +- 1 uA so whatever is driving all CF lines is doing so at a >> very low load level. Since the IDE An and IDE Dn lines all connected to the >> 8255 ports that probably explains why those lines may be OK. In my Toshiba >> TMP82C55A datasheet it shows a Voh of Vcc-0.8V for Ioh of -100uA. As long >> as the load seen by the 8255 is just one of two CF cards with a total >> leakage of +- 2 uA that would work. But any 8255 outputs driving TTL inputs >> may have a low or marginal Voh at least for Dn and An. >> >> I can see no reasons for use of the high power - high speed gates and the >> low value pull ups on the IORD, IOWR, CSn, and RESET lines. As I read the >> specs it looks like those gates can be 74LS00's with no pull up or much >> higher pull ups (50K ?). In addition if we do not need to switch the higher >> currents associated with the low value pull ups that will reduce noise >> levels on the board. >> >> I need to read the CF spec again and do a line by line gozinta versus >> gozouta analysis before reaching for the de-soldering braid and solder >> sucker. It is possible that I have completely misread the spec and if so I >> apologize for the confusion but right now I think there may be some >> low-hanging fruit that should be harvested. Even if what my initial look >> indicates proves correct there may be other issues. >> >> I will get back to everyone hopefully by late on the 18th. >> >> If anyone has reason to show me the error in my thinking please fire away >> - at my age my skin has absorbed many blasts and a little more will not >> hurt. >> >> Rich Leary >> >> -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
