John Can you post the GAL file as well - I like the way it looks now (guess I should have read the forum before sending last email to you). I think condensing things into the GAL may eliminate future timing problems and does allow a lot more tweaking if necessary.
Looking at proposed schematic without seeing equations, I think you are duplicating function in the 2 GALs. Think about what I proposed in my email. Use a 682 for the upper 8 address lines and use it as input into a 22v10 and then use the lower address lines and other S100 signals as input and derive the necessary signals. The way you have it now it looks like you are using duplicate signals like bsInp, bsOut, etc on both GALs. Dave On Thursday, February 12, 2015 at 12:38:37 AM UTC-6, monahanz wrote: > > Dave, I just looked into using two GAL's (22V10's). With that setup things > do indeed look simple/clean. Please see the attached schematic. > A few non obvious points. I buffer the S100 signals so only one LS load > per input per board (assuming these Lattice LGAL's ate LS loads). This > includes data line D0. > I added pSYNC to pin 1 of U102 in case the was a need to clock and use > registers (instead of computational outputs). > The GAL logic is simply the previous signals moved into the GAL. Is my > thinking OK on the 74LS373's > > The only catch with all this is two GAL's instead of one. What do people > think? > John > > > > On Tuesday, February 10, 2015 at 11:13:58 AM UTC-8, monahanz wrote: > >> Guy's I thinking of doing another run of our now, old, S100 bus IDE/CF >> card board. There are probably close to 150 of them out there by now. >> >> It's described here:- >> >> >> *http://s100computers.com/My%20System%20Pages/IDE%20Board/My%20IDE%20Card.htm* >> >> <http://s100computers.com/My%20System%20Pages/IDE%20Board/My%20IDE%20Card.htm> >> >> Hard to believe but the first board was back in 2010! >> >> >> >> While the V2 board seems to work fine for most people, there may be some >> things "not quite right" with the design for high bus speeds around 10MHz >> and with fast CPU's like the 80386 and with multi-sector reads with MSDOS >> etc. >> >> >> >> I decided the time was right to fine tune the board for another run, a V3 >> version. There are a few things I wanted to do. >> >> >> >> 1. I do not want to change the basic 8255 driven circuit and all the >> software I and others have over the years written for the board. Sure if I >> were to do it all over again I would probably have done it different using >> perhaps a faster Zilog PIO or an onboard fast fully dedicated Z80 (as for >> our ZFDC board) or Propeller etc. The NEC or OKI 82C55-2’s are dirt >> common and seem to be able to handle anything the CPU sends to them. >> >> >> >> 2. I want to hand lay down broad power traces to all the boards IC’s >> for more even power distribution – particularly to the power hungry HEX >> displays. >> >> >> >> 3. I have inserted a trace “Keep out Area” on the front of the board >> so there is no danger of the IDE adaptors touching a critical trace. >> >> >> >> 4. I added a single TO-3 V regulator (e.g. 78H05’S) capable of >> delivering high currents without overheating the board locally. Yes I know >> we should be going to the switching regulators, but this is often a first >> board for builders, wanted to keep it simple. >> >> >> >> 5. However I did bend the rules a little and add one 22V10 GAL. This >> greatly simplifies the board and really speeds up the port addressing and >> the potential drive select/reset issues some were having. I realize not >> everybody is familiar with GAL’s. For those people and beginners I will >> supply the pre-programmed Lattice 22V10 GAL. Will of course supply the >> PALASM code for others. Again these GAL’s are fairly common (Jameco #39159 >> for the 15ns variety). >> >> >> >> 6. I have switched over to using a 74LS00 (instead of the OC 7403’s) >> for the critical RD/WD circuit. This is based on (Roger & others) >> observations. Still a bit worried about this, but it’s a prototype can >> easily add pull-ups and a 7403. >> >> >> >> 7. People should be able to simply switch IC’s from the old board to >> this new one. Only a new GAL IC is required. >> >> >> >> 8. Last but least I relabeled much of the Silk Screen to be more >> relevant. For example placing IC numbers above their pin locations. >> >> >> >> I’m attaching a suggested schematic and a picture of the proposed V3 >> board. Could people take a look at it? Any suggestions etc. will be >> gratefully received. Dave in particular I would really appreciate your >> input. You have a keen eye for detecting potential issues and know this >> board well. I have added my complete working KiCAD file folder at the >> very bottom of the page of the above URL for anybody that has the time to >> look. >> >> >> >> >> >> >> > -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
