Hey, This is not an advertisement but an attempt to help folks to better understand networking HW. Some of you might know (and love 😊) “between 0x2 nerds” podcast Jeff Doyle and I have been hosting for a couple of years. Following up the discussion we have decided to dedicate a number of upcoming podcasts to networking HW, the topic where more information and better education is very much needed (no, you won’t have to sign NDA before joining 😊), we have lined up a number of great guests, people who design and build ASICs and can talk firsthand about evolution of networking HW, complexity of the process, differences between fixed and programmable pipelines, memories and databases. This Thursday (08/04) at 11:00PST we are joined by one and only Sharada Yeluri - Sr. Director ASIC at Juniper. Other vendors will be joining in the later episodes, usual rules apply – no marketing, no BS. More to come, stay tuned. Live feed: https://lnkd.in/gk2x2ezZ Between 0x2 nerds playlist, videos will be published to: https://www.youtube.com/playlist?list=PLMYH1xDLIabuZCr1Yeoo39enogPA2yJB7 Cheers, Jeff From: James Bensley On Tue, 26 Jul 2022 at 21:39, Lawrence Wobker <ljwob...@gmail.com> wrote: > So if this pipeline can do 1.25 billion PPS and I want to be able to forward 10BPPS, I can build a chip that has 8 of these pipelines and get my performance target that way. I could also build a "pipeline" that processes multiple packets per clock, if I have one that does 2 packets/clock then I only need 4 of said pipelines... and so on and so forth. Thanks for the response Lawrence. The Broadcom BCM16K KBP has a clock speed of 1.2Ghz, so I expect the J2 to have something similar (as someone already mentioned, most chips I've seen are in the 1-1.5Ghz range), so in this case "only" 2 pipelines would be needed to maintain the headline 2Bpps rate of the J2, or even just 1 if they have managed to squeeze out two packets per cycle through parallelisation within the pipeline. Cheers, James. |
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