On 9/30/23 01:36, William Herrin wrote:
If I were designing the product, I'd size the SRAM with that in mind. I'd also keep two full copies of the FIB in the outer DRAM so that the PPEs could locklessly access the active one while the standby one gets updated with changes from the RIB. But I'd design the router to gracefully fail if the FIB exceeded what the SRAM could hold. When a TCAM fills, the shortest prefixes are ejected to the router's main CPU. That fails pretty hard since the shortest prefixes tend to be among the most commonly used. By comparison, an SRAM cache tends to retain the most commonly used prefixes as an inherent part of how caches work, regardless of prefix length. It can operate close to full speed until the actively used routes no longer fit in the cache.
Well, not sure if you're aware, but starting Junos 21.2, Juniper are implementing FIB Compression on the PTX routers running Express 4 and Junos EVO.
We have some of these boxes in our network (PTX10001), and I have asked Juniper to provide a knob to allow us to turn it off, as it is currently going to ship as a default-on feature. I'd rather not be part of the potential mess that is going to come with the experimentation of that over the next decade.
Mark.
