I spin quite a few PCB designs at present where I work, using the latest incarnation of Orcad (very much a love / hate relationship). A few years ago when I was starting out at a (different) company with Orcad, I opted for "Arc" routing rather than the conventional 45/90 degree modes and had a wonderful time. It was never appreciated (I managed to avoid having to redo it at least) but the product using the board is still in production at a fab house many years later.
Pretty much agree on all of Terry's points though. Getting components in a nice even grid arrangement is always my OCD point, cant beat a matrix of 0603 parts on a board. I tend to keep the grids course until placed and then drop to 10 mil for routing... We tend to do prototypes and low volume though so run all our boards through Wurth in Germany, who do ENIG by default now. The boards look really pretty. Still miss this era though: <http://bunniefoo.com/ntw/ntw_feb_2014_b.jpg> - Alex On Friday, 19 August 2016 01:04:29 UTC+1, Terry S wrote: > > John, > > There's probably little I can teach you, it sounds like you are a seasoned > designer as well. But for the group, here is some of what I see on the eval > board that would not pass muster today. > > 1) Mid trace T's. Also off-angle T's in particular. These are frowned > upon, especially in modern fine line designs. The T creates acid traps in > the 90 degree corners. Much better to run traces out of and thru pads -- > the round pad effectively opens the corner and "softens" the acid traps. > > 2) 90s. For the same reasons, 90s are generally avoided. Virtually every > 90 can be done with 45s. > > 3) Pad exits at angles other than 45 or multiples thereof. It simply makes > for inefficient routing resource usage. Again, critical in higher density > designs. It's also ugly. > > 4) Pad exits off center from the pad. These create acute inside angles, > acid traps. Also 45s and other angle bends too close to pad exits. > > 5) Diode symbols done in copper -- why? Almost no other component polarity > is marked. Also the markings here are *under* the diodes -- not very > useful. Copper is for current - and sometimes heat. > > 6) IC pin 1 marking. Let's use a square pad. > > 7) Routing not following the golden rule -- horizontal on one layer, > vertical on the other. This is the rule you follow when routing, then break > during optimization. You break it to reduce vias. > > I could go on with what's wrong with the layout, but it's not really fair > to compare this design to a modern CAD generated design. This was done when > the tools didn't exist and iterations were difficult. > > Regarding HASL -- I consider that finish obsolete. Like you said, ugly for > lead free. Immersion Silver is a better option if you must avoid ENIG for > cost reasons. I never liked HASL even in the lead solder days -- too often > it caused the old glossy wet film solder masks to bubble & flake. But we > used it. > > Solder mask: The current standard is liquid photo-imageable. Dry film is > also still popular. > > Silkscreen: This is the subject of some controversy these days. Some > designers subscribe to the new "eliminate the silkscreen for production" > theory. I don't, but that's because I'm always the guy debugging the > design, not just doing the layout. I want that silkscreen. I want it when > I'm probing a board buried in a machine. I want it when a board comes back > from the field with a burned spot... and I want it when it's rework time or > UL testing time. I have never let my employer or client talk me into > eliminating the silkscreen - yet. It's such a small cost adder in > production, and believe me, your contract manufacturer (CM) likes to have > it too. > > Substrates: Too big a topic to cover here. But FR4 is obsolete.... there > are a wealth of choices, consult your CM and engineers.... > > Terry S > CID > > On Thursday, August 18, 2016 at 12:04:54 AM UTC-5, jrehwin wrote: >> >> > In the early 80's I was doing 8 mil lines & spaces, getting two traces >> between pads on .1" spacing. It was pushing the limit of the local board >> houses. It was also just the ticket for high speed memory boards for a >> couple decades, until the DDR stuff came along. Now 6 mil is considered >> large, 4 mil is the bottom size without paying for low yields. I still use >> 8 mil on boards that can afford it, from a density standpoint. >> >> I do 10/10 if it will fit, a lot of 8/8 and a few 6/6, but most of the >> stuff I design isn’t terribly tight. >> >> > Gold plating has been making a big comeback in recent years -- ENIG -- >> or electroless nickel immersion gold. It's a good finish for lead free >> solder. Almost everything I've done for 7 or 8 years now gets ENIG. At >> many board houses it's not even a premium cost adder. It's a soft finish -- >> not suitable for edge connectors. >> >> ENIG is much better for high lead count surface mount packages than HASL. >> It’s also pretty. I did one run of lead free HASL for a group that wanted >> lead free but didn’t want to spring for ENIG. It worked, but wasn’t as >> good looking. >> >> > PCB design has come a long way. I've been doing it 30 years now. There >> are things done on these early PCBs that we avoid like the plague now. >> >> Care to share? I’m always up to learn something new. I’ve been amazed >> at the things that are common knowledge one place and unheard-of at >> another. >> >> - John >> >> -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/f36abda2-6d01-4232-9ba7-ad948023300a%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
