I'm doubtful that latch-up is happening here, because it usually results in a short-circuit across the supply. Also, the problem as described happens after a few hours of operation, and not during power-up. I'm suspecting a hold-time marginality.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- >From my experience in chip design, latch-up is initiated when excess current is forced thru a pin. For most IC's, the only way to do this is by applying a voltage greater than Vcc or less than GND (ie, a negative voltage) to a signal pin. Usually, currents well-above 100mA are required to induce latch-up; not many datasheets spec the latch-up current, but you can use the short-circuit current as a guideline for your design. Latch-up can happen on input, output, and inout pins under the right circumstances. So, what can you do to prevent latch-up ? The highest-risk areas are mixed-voltage designs, where the supplies are not sequenced in a specific manner. If you have a +5V and +3.3V design, a diode forward-biased from the 3.3V supply to the 5V supply will provide a lot of protection as long as the 3.3V supply is brought-up first, and brought-down last. Also, the 3.3V supply must be able to provide sufficient current to hold-up the 5V rail until that supply comes up. Years ago we used this on desktop PCs that had a mix of 3.3V and 5.0V devices; we also had a string of 3 diodes from the 5V supply to the 3.3V supply, and that allowed supplies to come-up in any order. There were millions of PCs built with this approach back in the 90's and I'm not aware of any field returns root-caused to latch-up. If that wont work, you can add series resistors on signals between power domains to limit the current. Suppose you need to protect signals between 3.3V and 5V domains, and the current needs to be limited to 25mA (the output short-circuit current of an LM348 OP-amp). Be aware it takes at least a 'diode-drop' voltage difference (about 0.7V) to start forcing more current thru a CMOS pin. Knowing this, the series resistance should be at least R= (5 - 3.3 - 0.7)/25mA, or 40 ohms. This will affect circuit timing somewhat; if load-capacitance is around 25pF the signal-delay from the RC-network will be around 1 time-constant, which is 40*25 = 1000psec (1nsec) in this case. This assumes a 2.0V threshold for a 3.3V supply. Here is a brief paper from TI that discusses latch-up: http://www.ti.com/lit/wp/scaa124/scaa124.pdf -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/04727a2e-509a-4d35-9c2b-9454f3897082%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
