Fix a race in the receive NAPI, irq handling. The interrupt clear and the
start need to be separated. Otherwise there is a window between the last
frame received and the NAPI done level handling.
Skge will hang on SMP with aggressive irq balancing without this.
Signed-off-by: Stephen Hemminger <[EMAIL PROTECTED]>
--- skge.orig/drivers/net/skge.c 2006-02-20 10:47:32.000000000 -0800
+++ skge/drivers/net/skge.c 2006-02-20 10:47:36.000000000 -0800
@@ -2676,8 +2676,7 @@
/* restart receiver */
wmb();
- skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
- CSR_START | CSR_IRQ_CL_F);
+ skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
mmiowb();
*budget -= work_done;
@@ -2854,14 +2853,6 @@
local_irq_enable();
}
-static inline void skge_wakeup(struct net_device *dev)
-{
- struct skge_port *skge = netdev_priv(dev);
-
- prefetch(skge->rx_ring.to_clean);
- netif_rx_schedule(dev);
-}
-
static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
{
struct skge_hw *hw = dev_id;
@@ -2872,13 +2863,15 @@
status &= hw->intr_mask;
if (status & IS_R1_F) {
+ skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
hw->intr_mask &= ~IS_R1_F;
- skge_wakeup(hw->dev[0]);
+ netif_rx_schedule(hw->dev[0]);
}
if (status & IS_R2_F) {
+ skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
hw->intr_mask &= ~IS_R2_F;
- skge_wakeup(hw->dev[1]);
+ netif_rx_schedule(hw->dev[1]);
}
if (status & IS_XA1_F)
--
-
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