Walt wrote:

> Nope, it was the second one:  Skip phy power down...
> Let me know if can test any patches, etc.

It doesn't make sense. This code should have no effect on your
5702. With or without this patch, the 5702 will be powered down
the same with tg3_writephy(tp, MII_BMCR, BMCR_PDOWN) if WOL
is not enabled when you ifdown.

Also, for this code to have any effect, you must do ifdown or
suspend. So presumably the driver loaded fine at least once and
you get the failure during subsequent modprode. Is that right? But
the driver should behave the same on 5702 with or without the patch
if you follow the same sequence.

You can also try to bypass this code by setting WOL. Use
ethtool -S eth0 wol g to enable WOL and the phy will not be powered
down.

I'll look into this some more later today. Thanks.


> 
> This is the problem code:
> $diff -u tg3.c.good tg3.c
> --- tg3.c.good  2006-03-23 20:08:55.000000000 -0800
> +++ tg3.c       2006-03-24 04:19:59.000000000 -0800
> @@ -1148,6 +1148,19 @@
>  static int tg3_nvram_lock(struct tg3 *);
>  static void tg3_nvram_unlock(struct tg3 *);
> 
> +static void tg3_power_down_phy(struct tg3 *tp)
> +{
> +       /* The PHY should not be powered down on some chips because
> +        * of bugs.
> +        */
> +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
> +           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
> +           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
> +            (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
> +               return;
> +       tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
> +}
> +
>  static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
>  {
>         u32 misc_host_ctrl;
> @@ -1327,8 +1340,7 @@
>                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
>                                      MII_TG3_EXT_CTRL_FORCE_LED_OFF);
>                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
> -                       if (GET_ASIC_REV(tp->pci_chip_rev_id) !=
ASIC_REV_5700)
> -                               tg3_writephy(tp, MII_BMCR,
BMCR_PDOWN);
> +                       tg3_power_down_phy(tp);
>                 }
>         }
> 
> 

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