On 31.10.2016 18:12, Jiri Pirko wrote: >> > >> >In the naive implementation only pipelines that map 1:1 will work. Maybe >> >this is what Alexei is noticing? > P4 is ment to program programable hw, not fixed pipeline.
Is it realistic to assume that future hardware might be programmed with a proprietary (FPGA-alike) bitstream where a generic API wouldn't fit anymore? I could imagine vendors shipping a higher abstracted VHDL/Verilog compiler in the future and expect the kernel just forward it to the hardware as-is. Bye, Hannes
