From: Ganesh Goudar <ganes...@chelsio.com> Date: Mon, 20 Mar 2017 14:22:38 +0530
> From: Arjun Vynipadath <ar...@chelsio.com> > > We are using the smallest padding boundary (8 bytes), which isn't > smaller than the Memory Controller Read/Write Size > > We get best performance in 100G when the Packing Boundary is a multiple > of the Maximum Payload Size. Its related to inefficient chopping of DMA > packets by PCIe, that causes more overhead on bus. So driver is helping > by making the starting address alignment to be MPS size. > > We will try to determine PCIE MaxPayloadSize capabiltiy and set > IngPackBoundary based on this value. If cache line size is greater than > MPS or determinig MPS fails, we will use cache line size to determine > IngPackBoundary(as before). > > Signed-off-by: Arjun Vynipadath <ar...@chelsio.com> > Signed-off-by: Casey Leedom <lee...@chelsio.com> > Signed-off-by: Ganesh Goudar <ganes...@chelsio.com> Applied, thank you.
