From: Andrew Lunn <and...@lunn.ch> Date: Thu, 15 Jun 2017 19:03:11 +0200
> On Thu, Jun 15, 2017 at 12:13:58PM -0400, Vivien Didelot wrote: >> This patch series is the 2/3 step of the register definitions cleanup. >> It brings no functional changes. >> >> It prefixes and documents all Global (1) registers with MV88E6XXX_G1_ >> (or a specific model like MV88E6352_G1_STS_PPU_STATE), and prefers a >> 16-bit hexadecimal representation of the Marvell registers layout. >> >> The next and last patchset will prefix the Global 2 registers. > > Reviewed-by: Andrew Lunn <and...@lunn.ch> Series applied, thanks everyone.
