On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote: > To clear Speed Selection in MDIO control register(0x10), > ie, clear bits 6 and 13 to zero while keeping other bits same. > Before AND operation,The Mask value has to be perform with bitwise NOT > operation (ie, ~ operator) > > This patch clears current speed selection before writing the > new speed settings to gmii2rgmii converter
Hi Fahad I expect you will find other issues with this driver. I pointed some out at the time it is submitted, but the developers went quiet as soon as it was accepted. Anyway, please ensure David Miller <da...@davemloft.net> gets a copy. The subject line should be: [PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed register. and include a fixes tag: Fixes: f411a6160bd4 ("net: phy: Add gmiitorgmii converter support") Reviewed-by: Andrew Lunn <and...@lunn.ch> Andrew