On February 14, 2018 8:07:11 AM PST, Daniel Schultz <d.schu...@phytec.de> wrote: >From: Wadim Egorov <w.ego...@phytec.de> > >The DP83867 has a muxing option for the CLK_OUT pin. It is possible >to set CLK_OUT for different channels. >Create a binding to select a specific clock for CLK_OUT pin. > >Signed-off-by: Wadim Egorov <w.ego...@phytec.de> >Signed-off-by: Daniel Schultz <d.schu...@phytec.de> >--- >Changes: > v2: > Added check if clk_output_sel has a valid value > Only write the clock ouput register if a musing is desired > v3: > - > > drivers/net/phy/dp83867.c | 19 +++++++++++++++++++ > include/dt-bindings/net/ti-dp83867.h | 14 ++++++++++++++ > 2 files changed, 33 insertions(+) > >diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c >index c1ab976..a862194 100644 >--- a/drivers/net/phy/dp83867.c >+++ b/drivers/net/phy/dp83867.c >@@ -75,6 +75,8 @@ > > #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 > #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f >+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) >+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 >
Nit: it looks like you could use the shift constant you define for defining the mask as well. Other than that: Reviewed-by: Florian Fainelli <f.faine...@gmail.com> -- Florian
