Hi Heiner, On 3/5/2019 2:18 AM, Heiner Kallweit wrote: > On 04.03.2019 15:48, S-k, Shyam-sundar wrote: >> Hi Heiner, >> >> We noticed that, the recent changes for CL45 in net-next tree causing >> regression on AMD platforms. The following is the commit: >> >> 3ce2a02 net: phy: marvell10g: check for newly set aneg >> >> Now, I see that, this code is moved to phy-c45.c with newer commit >> >> 1af9f16 net: phy: add genphy_c45_check_and_restart_aneg >> >> With this change, the link never comes up. Can you please a re-look once >> before it enters mainline? >> >> Thanks, >> >> Shyam >> > Hi Shyam, > > thanks for the report. However the description quite vague, therefore I'd > appreciate the following details: > > - The mentioned patch affects Marvell 10G PHY's only. Could you please > provide: > - exact PHY model you're using Yes, we have on-board Marvell 88X3310 chip, which works as external PHY for AMD Ethernet controller. > - interface mode you're using RJ45. > - link speed you expect and advertised speeds from both sides Both advertised and link speeds are 1G SGMII > > - Some details regarding "AMD platform" would be helpful. What kind of board > is it? > > - There's a known issue in genphy_c45_an_config_aneg(), however I'm not sure > whether it could be related > to your issue. Could you please test the following patch whether it fixes > the issue for you? > https://patchwork.ozlabs.org/patch/1051291/
Thank you very much! This patch fixes the problem. -Shyam
