It is better to centralize all sub-register zero extension checks into an independent file.
This patch takes the first step to move existing sub-register zero extension checks into subreg.c. Acked-by: Jakub Kicinski <[email protected]> Reviewed-by: Quentin Monnet <[email protected]> Signed-off-by: Jiong Wang <[email protected]> --- tools/testing/selftests/bpf/verifier/basic_instr.c | 39 ---------------------- tools/testing/selftests/bpf/verifier/subreg.c | 39 ++++++++++++++++++++++ 2 files changed, 39 insertions(+), 39 deletions(-) create mode 100644 tools/testing/selftests/bpf/verifier/subreg.c diff --git a/tools/testing/selftests/bpf/verifier/basic_instr.c b/tools/testing/selftests/bpf/verifier/basic_instr.c index 4d84408..ed91a7b 100644 --- a/tools/testing/selftests/bpf/verifier/basic_instr.c +++ b/tools/testing/selftests/bpf/verifier/basic_instr.c @@ -132,42 +132,3 @@ .prog_type = BPF_PROG_TYPE_SCHED_CLS, .result = ACCEPT, }, -{ - "and32 reg zero extend check", - .insns = { - BPF_MOV64_IMM(BPF_REG_0, -1), - BPF_MOV64_IMM(BPF_REG_2, -2), - BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2), - BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), - BPF_EXIT_INSN(), - }, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, - .result = ACCEPT, - .retval = 0, -}, -{ - "or32 reg zero extend check", - .insns = { - BPF_MOV64_IMM(BPF_REG_0, -1), - BPF_MOV64_IMM(BPF_REG_2, -2), - BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2), - BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), - BPF_EXIT_INSN(), - }, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, - .result = ACCEPT, - .retval = 0, -}, -{ - "xor32 reg zero extend check", - .insns = { - BPF_MOV64_IMM(BPF_REG_0, -1), - BPF_MOV64_IMM(BPF_REG_2, 0), - BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2), - BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), - BPF_EXIT_INSN(), - }, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, - .result = ACCEPT, - .retval = 0, -}, diff --git a/tools/testing/selftests/bpf/verifier/subreg.c b/tools/testing/selftests/bpf/verifier/subreg.c new file mode 100644 index 0000000..edeca3b --- /dev/null +++ b/tools/testing/selftests/bpf/verifier/subreg.c @@ -0,0 +1,39 @@ +{ + "or32 reg zero extend check", + .insns = { + BPF_MOV64_IMM(BPF_REG_0, -1), + BPF_MOV64_IMM(BPF_REG_2, -2), + BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2), + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), + BPF_EXIT_INSN(), + }, + .prog_type = BPF_PROG_TYPE_SCHED_CLS, + .result = ACCEPT, + .retval = 0, +}, +{ + "and32 reg zero extend check", + .insns = { + BPF_MOV64_IMM(BPF_REG_0, -1), + BPF_MOV64_IMM(BPF_REG_2, -2), + BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2), + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), + BPF_EXIT_INSN(), + }, + .prog_type = BPF_PROG_TYPE_SCHED_CLS, + .result = ACCEPT, + .retval = 0, +}, +{ + "xor32 reg zero extend check", + .insns = { + BPF_MOV64_IMM(BPF_REG_0, -1), + BPF_MOV64_IMM(BPF_REG_2, 0), + BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2), + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), + BPF_EXIT_INSN(), + }, + .prog_type = BPF_PROG_TYPE_SCHED_CLS, + .result = ACCEPT, + .retval = 0, +}, -- 2.7.4
