On Tuesday 30 January 2007 11:30 pm, Linas Vepstas wrote:
> Shifting to the right by 5 bits has no effect on the result
> of this conditional. Either the bit is set, or its not.
> There is no need to shift.
>
> > + if ( (phy_reg & 0x0020) >> 7 ) {
You are right, I corrected this.
> The result here will always be zero, since the bit,
> if set, will be shifted off the end. Bits on the lef
> are padded with zero. Ergo, this is a bug.
You are right, wrong bit. I corrected this.
Jens
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