On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote:
> The RGMII control register at 0x32 indicates the states for the bits
> RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
>
> RGMII Transmit/Receive Clock Delay
> 0x0 = RGMII transmit clock is shifted with respect to transmit/receive
> data.
> 0x1 = RGMII transmit clock is aligned with respect to transmit/receive
> data.
>
> This commit fixes the inversed behavior of these bits
>
> Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration")
I Daniel
I would like to see some sort of response from Dan Murphy about this.
Andrew
