On Fri, 2015-07-03 at 16:18 +0000, David Laight wrote:
> Even on x86 aligning the ethernet receive data on a 4n+2
> boundary is likely to give marginally better performance
> than aligning on a 4n boundary.
You are coming late to the party.
Intel guys decided to change NET_IP_ALIGN to 0 (it was 2 in the past)
commit ea812ca1b06113597adcd8e70c0f84a413d97544
Author: Alexander Duyck <alexander.h.du...@intel.com>
Date: Tue Jun 29 18:38:00 2010 +0000
x86: Align skb w/ start of cacheline on newer core 2/Xeon Arch
x86 architectures can handle unaligned accesses in hardware, and it has
been shown that unaligned DMA accesses can be expensive on Nehalem
architectures. As such we should overwrite NET_IP_ALIGN to resolve
this issue.
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Ingo Molnar <mi...@redhat.com>
Cc: "H. Peter Anvin" <h...@zytor.com>
Cc: x...@kernel.org
Signed-off-by: Alexander Duyck <alexander.h.du...@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirs...@intel.com>
Acked-by: H. Peter Anvin <h...@zytor.com>
Signed-off-by: David S. Miller <da...@davemloft.net>
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