Hi Dan,
On 10/26/2015 08:16 PM, dan.street...@canonical.com wrote:
> From: Dan Streetman <dan.street...@canonical.com>
>
> The driver currently waits 1us after issuing a RST, but the spec
> requires it to wait 1ms.
>
> Signed-off-by: Dan Streetman <dan.street...@canonical.com>
> Signed-off-by: Dan Streetman <ddstr...@ieee.org>
> ---
> drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
> b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
> index 4e75843..147bc65 100644
> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
> @@ -113,7 +113,12 @@ mac_reset_top:
>
> /* Poll for reset bit to self-clear indicating reset is complete */
> for (i = 0; i < 10; i++) {
> - udelay(1);
> + /* sec 8.2.4.1.1 :
> + * programmers must wait approximately 1 ms after setting before
> + * attempting to check if the bit has cleared or to access (read
> + * or write) any other device register.
> + */
> + mdelay(1);
Since ixgbe_reset_hw_x540() goes on to msleep(100) immediately after this
busy-wait loop, this should instead be:
msleep(1);
Regards,
Peter Hurley
> ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
> if (!(ctrl & IXGBE_CTRL_RST_MASK))
> break;
>
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