On 2015-11-03, at 6:43 PM, Guy Harris wrote: > > On Nov 3, 2015, at 3:03 PM, Helge Deller <del...@gmx.de> wrote: > >> Sadly it's nowhere clearly documented how big the L1 cacheline of parisc >> really is. > > To which particular PA-RISC processor are you referring? It might not be the > same on all processors. > > If openpa.net is to be believed, then: > > The 7100LC has 32 byte cache lines on the off-chip cache: > > http://www.openpa.net/pa-risc_processor_pa-7100lc.html > > and the 8500 has "32 or 64 Byte cache line size", which may be referring to > the on-chip caches: > > http://www.openpa.net/pa-risc_processor_pa-8500.html
Yes, this is correct but these numbers relate to the memory interface. The PA8800 and PA8900 have 128 byte memory interfaces. These numbers are reported by firmware PDC calls. This whole discussion started when I suggested that we needed to bump L1_CACHE_BYTES to 128 bytes on PA8800 and PA8900 processors. -- John David Anglin dave.ang...@bell.net -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
