Jeremy Harris writes: > To attack the first problem above, perhaps we should ask cpu designers > for data-breakpoint *range* [1] facilities? [...] > [1], [2], [3] These may be patentable ideas. Since I no longer > work for Sun, they are hereby placed in the public > domain, with no restrictions.
Motorola would likely beg to differ on your disclosure for [1]. Hardware range breakpoints and even breakpoints with conditional (and/or) logic have been a standard part of the PowerQUICC family for a long time -- at least since the MPC860, more than ten years ago. The idea is almost certainly older than that. (Didn't VM/CP also have range facilities?) The 860 had four I-address, two L-address, and two L-data comparators, each with ==, !=, >, and <. The L-data comparators also had signed/unsigned modes and byte masks. These comparators fed into a programmable and/or logic structure. If you're interested, see chapter 44 in the MPC860UM [user's manual]. It'd be nice if the CPUs we ordinarily used had those features, but they're certainly not new inventions. -- James Carlson, KISS Network <[EMAIL PROTECTED]> Sun Microsystems / 1 Network Drive 71.232W Vox +1 781 442 2084 MS UBUR02-212 / Burlington MA 01803-2757 42.496N Fax +1 781 442 1677 _______________________________________________ networking-discuss mailing list [email protected]
